ILA.1

Check that the /R/ and /A/ characters are transmitted at the beginning and end of each multiframe.

Verify that four multiframes are transmitted in ILAS phase and receiver detects the initial lane alignment sequence correctly.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]
• jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

• sync_n
• jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data. The 32-bit data bus for is divided into 4 octets.

Check the following status in the AD9162 regis-ters:

• Frame Synchronization
• Initial Lane Synchronization

• The /R/ character or K28.0 (0x1C) is transmitted at the jesd204_tx_pcs_data bus to mark the beginning of multiframe.
• The /A/ character or K28.3 (0x7C) is transmitted at the jesd204_tx_pcs_data bus to mark the end of each multiframe.
• The sync_n and jesd204_tx_int signals are deasserted.
• The jesd204_tx_pcs_kchar_data signal is asserted when-ever control characters like /K/, /R/, /Q/ or /A/ characters are transmitted.
• The “Frame and Initial Lane Synchronization” status for all lanes should be asserted in the AD9162 registers 0x471 and 0x473 respec-tively.

ILA.2

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]

The following signal in <ip_variant_name>.v is tapped:

• jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

The system console accesses the following JESD CSR registers:

• ilas_data1
• ilas_data2

The content of 14 configuration octets in second multiframe is stored in the above 32-bit registers.

Check the following status and error in the AD9162 register:

• Good Checksum
• Configuration Mismatch Error

• The /R/ character is fol-lowed by /Q/ character or K28.4 (0x9C) in the jesd204_tx_pcs_data at the beginning of second multiframe.
• The jesd204_tx_int is deasserted if there is no error.
• The JESD204B parameters read from ilas_data1, ilas_data2 registers are the same as the parameters set in the JESD204B IP Core Qsys parameter editor.
• The “Link Configuration Mismatch Error” in the AD9162 register 0x4BB should not be asserted and the “Good Checksum” status for the AD9162 register 0x472 should be asserted.

ILA.3

Verify that the receiver successfully enters user data phase.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]

The following signals in <ip_variant_name>.v are tapped:

• jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

The system console accesses the JESD CSR register - tx_err.

Check the following errors in the AD9162 register:

• Lane FIFO Full
• Lane FIFO Empty

• When scrambler is turned off, the first user data is transmitted after the last /A/ character, which marks the end of the 4th mul-tiframe transmitted.¹
• Bits 2 and 3 of the JESD tx_err register are not set to “1”.
• The “Lane FIFO Full” and “Lane FIFO Empty” in the AD9162 registers 0x30C and 0x30D should not be asserted.
• The jesd204_tx_int is deasserted if there is no error.