AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

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ID 683452
Date 12/06/2016
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core and AD9162 Hardware Checkout Report
1. JESD204B IP Core and AD9162 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transceiver Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B IP Core and AD9162 Hardware Checkout Report

1.3.2. Transceiver Transport Layer

To verify the data integrity of the payload data stream through the TX JESD204B IP core and transport layer,the DAC’s JESD core is configured to check short transport layer test pattern that is transmitted from FPGA’s test pattern generator. The DAC JESD core checks the transport layer test patterns based on F = 1, 2, 4 or 8 configuration. The short test pattern has a duration of one frame period and is repeated continu- ously for the duration of the test.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a sinewave. Connect an oscilloscope to observe the waveform at the DAC analog channels.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using Short Transport Layer Pattern CheckerThe SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Check the transport layer mapping using STPL test pattern.

The following signals in altera_jesd204_transport_tx_top.sv are tapped:

  • jesd204_tx_data_valid
  • jesd204_tx_data_ready

The following signals in jesd204b_ed.sv are tapped:

  • jesd204_tx_int

The txframe_clk is used as the SignalTap II sampling clock.

Check the following status in the DAC:

  • STPL teststatus
  • The jesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The STPL error for all DACs is checked in DAC register 0x32F and jesd204_tx_int signal should be deasserted.
TL.2 Verify the data transfer from digital to analog domain Enable sinewave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.
  • A monotone sinewaveis observed on the oscilloscope
Level Two Title