AN-785: Altera JESD204B IP Core and ADI AD9162 Hardware Checkout Report

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ID 683452
Date 12/06/2016
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Core and AD9162 Hardware Checkout Report
1. JESD204B IP Core and AD9162 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transceiver Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B IP Core and AD9162 Hardware Checkout Report

1.3.1.1. Code Group Synchronization (CGS)

Table 1.  CGS Test CasesL in the following table indicates the number of lanes.
Test Case Objective Description Passing Criteria

CGS.1

 Check that /K/ characters are transmitted when sync_n is asserted.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

Check the Code Group Synchronization Status status in the AD9162 Register.

  • /K/ character or K28.5 (0xBC) is transmitted at each octet of the jesd204_tx_pcs_data bus when the receiver asserts the sync_n signal.
  • The jesd204_tx_pcs_kchar_data signal is asserted when-ever control characters like /K/ characters are transmitted.
  • The jesd204_tx_int is deas-serted if there is no error.
  • The “Code Group Synchronization Status” for all lanes should be asserted in DAC Register 0x470.

CGS.2

 Check that /K/ characters are transmitted after sync_n is deasserted but before the start of multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

  • jesd204_tx_pcs_data[(L*32)-1:0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

  • sync_n
  • tx_sysref
  • jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by 32-bit data bus in the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into 4 octets.

Check the following error in the AD9162 reg-ister:

  • 8b/10b Not-in-Table Error
  • 8b/10b Disparity Error
  • The /K/ character transmission continues for at least 1 frame plus 9 octets.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • The “8b/10b Not-in-Table Error” and “8b/10b Disparity Error” in AD9162 registers 0x46E and 0x46D respectively should not be asserted.
Level Two Title