Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Overview of the Intel® FPGA Power and Thermal Calculator 3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 4. Intel® FPGA Power and Thermal Calculator Graphical User Interface 5. Intel® FPGA Power and Thermal Calculator Pages 6. Factors Affecting the Accuracy of the Intel® FPGA PTC 7. Intel® FPGA Power and Thermal Calculator User Guide Archive 8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
2. Overview of the Intel® FPGA Power and Thermal Calculator x
2.1. Accessing the Intel FPGA Power and Thermal Calculators 2.2. Intel® FPGA PTC Power Model Status 2.3. Definitions of Power Terms Used in this Document
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
3.1. Estimating Power Before Starting the FPGA Design 3.2. Estimating Power While Creating the FPGA Design 3.3. Estimating Power After Completing the FPGA Design 3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.5. Estimating Power for Dual-Core Devices
3.2. Estimating Power While Creating the FPGA Design x
3.2.1. Importing a .qptc File Generated in the Intel® Quartus® Prime Power Analyzer Controls to Simplify the Imported Design
3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator x
3.4.1. Entering Hierarchy Information Into the Intel® FPGA PTC 3.4.2. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
4.1. Intel® FPGA PTC Select Family Dialog Box 4.2. Intel® FPGA PTC Primary GUI Components 4.3. Deleting Rows from Data Entry Pages 4.4. Intel® FPGA PTC - IP Wizard
4.2. Intel® FPGA PTC Primary GUI Components x
4.2.1. Intel® FPGA PTC Data Entry Pages 4.2.2. Intel® FPGA PTC Hierarchy Manager 4.2.3. Intel® FPGA PTC Field Types 4.2.4. Intel® FPGA PTC Data Entry Error Messages
4.2.3. Intel® FPGA PTC Field Types x
4.2.3.1. Intel® FPGA PTC Input Field Dependencies
5. Intel® FPGA Power and Thermal Calculator Pages x
5.1. Intel® FPGA PTC - Power Summary 5.2. Intel® FPGA PTC - Common Page Elements 5.3. Intel® FPGA PTC - Main Page 5.4. Intel® FPGA PTC - Logic Page 5.5. Intel® FPGA PTC - RAM Page 5.6. Intel® FPGA PTC - DSP Page 5.7. Intel® FPGA PTC - Clock Page 5.8. Intel® FPGA PTC - PLL Page 5.9. Intel® FPGA PTC - I/O Page 5.10. Intel® FPGA PTC - Transceiver Page 5.11. Intel® FPGA PTC - HPS Page 5.12. Intel® FPGA PTC - Crypto Page 5.13. Intel® FPGA PTC - HBM Page 5.14. Intel® FPGA PTC - Thermal Page 5.15. Intel® FPGA PTC - Report Page
5.3. Intel® FPGA PTC - Main Page x
5.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
5.10. Intel® FPGA PTC - Transceiver Page x
5.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
6. Factors Affecting the Accuracy of the Intel® FPGA PTC x
6.1. Toggle Rate 6.2. I/O Bank Allocation
1. Answers to Top FAQs
2. Overview of the Intel® FPGA Power and Thermal Calculator
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface
5. Intel® FPGA Power and Thermal Calculator Pages
6. Factors Affecting the Accuracy of the Intel® FPGA PTC
7. Intel® FPGA Power and Thermal Calculator User Guide Archive
8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

3.2.1. Importing a .qptc File Generated in the Intel® Quartus® Prime Power Analyzer

If your design is partially complete and you have run the Intel® Quartus® Prime Power Analyzer, it has created a .qptc file, which you can import into the Intel® Quartus® Prime Power Analyzer (PTC).

You can invoke the Import dialog box, by clicking File > Import, or by clicking the Import button in the Hierarchy Manager.

The Import operation appends the imported data to all existing sheets, as appropriate. To overwrite an existing design, use File > Open.

Figure 2. Import File from Quartus Power Analyzer Dialog Box

The name rendered in italics at the top of the Hierarchy Node column is the name of the file to be imported. The remainder of the rows are populated with the contents of the file exported from the Intel® Quartus® Prime Power Analyzer.

You can expand or collapse the display of a given hierarchy level by clicking on the arrow to the left of its hierarchy node name or by pressing the left or right arrow keys on your keyboard.

The check box to the left of each hierarchy name allows you to include or exclude that hierarchy level from being imported into the PTC. Turn on a given check box to include its corresponding hierarchy level, or turn off the check box to exclude its level.

Note:
  1. If you turn on (check) a given hierarchy node, then all of its descendant nodes are also turned on.
  2. If you turn off (uncheck) a given node, then none of its descendants are turned on.
  3. If you turn on some of a given node's descendant nodes, then the parent node is partially turned on.
  4. Turning a given node on or off does affect the status of its descendants, and might affect the status of its parents.
Table 4.  Import File from Quartus Power Analyzer Information
Column Heading Description
Hierarchy Node Shows the names of the instances in the imported design, in a nested hierarchy.
Entity Name Shows the entity name of the corresponding instance from the Hierarchy Node column.
Instance Dynamic Power (W) Shows the estimated dynamic power of this entity instance, not including the power consumed by its descendants.
Cumulative Dynamic Power (W) Shows the estimated dynamic power of this entity instance, including the power consumed by its descendants.
Relative Dynamic Power (%) Shows the estimated dynamic power of this entity instance, including the power consumed by its descendants, as a percentage of the design's total power. The relative dynamic power of the top-level instance is 100%.
Note: You can click on any of the column headings to sort the table by the values in that column.

When you import a .qptc file, the Entity Name and Full Hierarchy Name of any blocks associated with a design hierarchy are automatically imported into those fields in the PTC.

Controls to Simplify the Imported Design

The controls at the right side of the dialog box allow you to flatten the imported design, effectively shrinking the design hierarchy to simplify the way it is represented in the PTC.

Table 5.  Import File from Quartus Power Analyzer Controls
Control Description
Flatten design hierarchy Click this check box to enable and disable design flattening. When this box is disabled, the controls below it are also disabled.
Note: Design flattening is a process by which hierarchical instances with cumulative power below a specified threshold are merged into their parent instances, thereby simplifying the design imported into the PTC, and making it easier for the PTC to model the design.
Threshold Provides a visual control for setting the flattening threshold. Move the slider fully to the left for no flattening, or fully to the right for maximum flattening.
Relative Allows you to specify a flattening threshold as a percentage of cumulative power.
Absolute Allows you to specify a flattening threshold in terms of absolute dynamic power, measured in watts. The valid range of values is from 0 W to the full dynamic power estimate included in the Intel® Quartus® Prime Power Analyzer report.

For more information about generating a .qptc file in the Intel® Quartus® Prime Power Analyzer, refer to the Intel® Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization.

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