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Ixiasoft
1.1. F-Tile Ethernet Intel® FPGA Hard IP v16.0.0
1.2. F-Tile Ethernet Intel® FPGA Hard IP v15.0.0
1.3. F-Tile Ethernet Intel® FPGA Hard IP v14.0.0
1.4. F-Tile Ethernet Intel® FPGA Hard IP v12.0.0
1.5. F-Tile Ethernet Intel® FPGA Hard IP v11.0.0
1.6. F-Tile Ethernet Intel® FPGA Hard IP v10.0.0
1.7. F-Tile Ethernet Intel® FPGA Hard IP v9.0.0
1.8. F-Tile Ethernet Intel® FPGA Hard IP v8.0.0
1.9. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0
1.10. F-Tile Ethernet Intel® FPGA Hard IP v6.0.0
1.11. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0
1.12. F-Tile Ethernet Intel® FPGA Hard IP v4.0.0
1.13. F-Tile Ethernet Intel® FPGA Hard IP v3.0.0
1.14. F-Tile Ethernet Intel® FPGA Hard IP v2.0.0
1.15. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
1.16. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
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Ixiasoft
1.10. F-Tile Ethernet Intel® FPGA Hard IP v6.0.0
Quartus® Prime Version | Description | Impact |
---|---|---|
22.2 | Added new parameter: Include Deterministic Latency Interface. The hardware support is not available in the current release. |
When enabled, generates the deterministic latency interface ports in FlexE mode. |
Added new parameter: Enable TX Packing. | Available when client interface is set to MAC segmented mode with no PTP. When PTP is disabled, the TX packing module for MAC segmented interface supports a rate range of 40G to 400G. |