F-Tile Ethernet Intel® FPGA Hard IP Release Notes

Download PDF
ID 683443
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes x
1.1. F-Tile Ethernet Intel® FPGA Hard IP v16.0.0 1.2. F-Tile Ethernet Intel® FPGA Hard IP v15.0.0 1.3. F-Tile Ethernet Intel® FPGA Hard IP v14.0.0 1.4. F-Tile Ethernet Intel® FPGA Hard IP v12.0.0 1.5. F-Tile Ethernet Intel® FPGA Hard IP v11.0.0 1.6. F-Tile Ethernet Intel® FPGA Hard IP v10.0.0 1.7. F-Tile Ethernet Intel® FPGA Hard IP v9.0.0 1.8. F-Tile Ethernet Intel® FPGA Hard IP v8.0.0 1.9. F-Tile Ethernet Intel® FPGA Hard IP v7.0.0 1.10. F-Tile Ethernet Intel® FPGA Hard IP v6.0.0 1.11. F-Tile Ethernet Intel® FPGA Hard IP v5.0.0 1.12. F-Tile Ethernet Intel® FPGA Hard IP v4.0.0 1.13. F-Tile Ethernet Intel® FPGA Hard IP v3.0.0 1.14. F-Tile Ethernet Intel® FPGA Hard IP v2.0.0 1.15. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 1.16. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
1. F-Tile Ethernet Intel FPGA Hard IP Release Notes

1.1. F-Tile Ethernet Intel® FPGA Hard IP v16.0.0

Table 1.  v16.0.0 2024.11.04
Quartus® Prime Version Description Impact
24.3 Added new parameter: Enable Signal tap for debug 1. When enabled, generates a Signal Tap File (STP) used for debugging. Applicable for Ethernet design examples generation.
Disabled the port i_tx_pfc for 200G and 400G data rates. Support for the i_tx_pfc port at all data rates is enabled only when using OPNs with the suffix VB or VC.
IP bug fixes. You must regenerate the IP.
1 This parameter is not available when AN/LT is enabled. If you enable AN/LT along with the Ethernet toolkit, the IP automatically generates an STP file during the design example generation.
Level Two Title