JESD204B Intel® FPGA IP User Guide

Download PDF
ID 683442
Date 5/05/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

5.2. Programmable RBD Offset

In the RX IP core, the programmable RBD offset provides flexibility for an early RBD release to optimize the latency through the IP core. You can configure the RBD offset using the csr_rbd_offset field in the syncn_sysref_ctrl register.

You must set a safe RBD offset value to ensure deterministic latency from one power cycle to another power cycle. Follow these steps to set a safe RBD offset value:

  1. Read the RBD count from the csr_rbd_count field in rx_status0 register. Record the value.
  2. Power cycle the JESD204B subsystem, which consists of the FPGA and converter devices.
  3. Read the RBD count again and record the value.
  4. Repeat steps 1 to 3 at least 5 times and record the RBD count values.
  5. Set the csr_rbd_offset accordingly with one LMFC count tolerance.
  6. Perform multiple power cycles and make sure lane deskew error does not occur using this RBD offset value.

The RBD count must be fairly consistent, within 2 counts variation from one power cycle to another power cycle. In the following examples, the parameter values are L > 1, F=1 and K=32. The legal values of the LMFC counter is 0 to ((FxK/4)-1), which is 0 to 7. In Figure 27 , the latest arrival lane variation falls within 1 local multiframe period. In this scenario, if latency is not a concern, you can leave the default value of csr_rbd_offset=0, which means the RBD elastic buffer is released at the LMFC boundary. In Figure 28 , the latest arrival lane variation spans across 2 local multiframes; the latest arrival lane variation happens before and after the LMFC boundary. In this scenario, you need to configure the RBD offset correctly to avoid lane deskew error as indicated in bit 4 of rx_err0 register.

Figure 27. Early RBD Release Opportunity for Latest Arrival Lane Within One Local Multi Frame ScenarioIn this example, the SYSREF pulse at rx_sysref port of the IP core is sampled by the internal register. After 2 link clock cycles, the LMFC counter resets. The delay from SYSREF sampled high to LMFC counter resets is deterministic. The transition of /K/ character to /R/ character marks the beginning of ILAS phase. The number of LMFC count of the /R/ character relative to the next LMFC boundary in the latest arrival lane is reported as the RBD count. In the first power cycle, the /R/ character is received at 4 LMFC counts before the next LMFC boundary, hence the RBD count = 4. In the second power cycle, the /R/ character is received at 3 LMFC counts before next LMFC boundary, hence the RBD count = 3. In five power cycles, the RBD count varies from 3 to 5. Since there are limited number of power cycles and boards for characterization, 1 LMFC count tolerance is allocated as a guide to set early RBD release opportunity. Hence, setting csr_rbd_offset = 1 can safely release the elastic buffer 1 LMFC count earlier at LMFC count 7 before the next LMFC boundary. A lane de-skew error occurs when the RBD elastic buffer is released before the latest arrival lane.
Figure 28. Early RBD Release Opportunity for Latest Arrival Lane Across Two Local Multi Frames ScenarioIn this example, the RBD count varies from 7 to 1; the /R/ character is received at the previous local multiframe when the RBD count = 1; the /R/ character is received at the current local multiframe when the RBD count = 0 and 7. In this scenario, deterministic latency is not guaranteed because the RBD elastic buffer is released either at the current LMFC boundary when the RBD count = 0 and 1, or one local multiframe period later at the next LMFC boundary when the RBD count = 7. You can fix this issue by setting the RBD offset so that the RBD elastic buffer is always released at the next local multiframe. Setting csr_rbd_offset = 5 forces the release of RBD elastic buffer 5 LMFC counts before the next LMFC boundary. This corresponds to LMFC count of 3 at the current local multiframe. In this scenario, setting csr_rbd_offset not only optimizes user data latency through the IP core, it also resolves the deterministic latency issue.

In the example above, lane deskew error happens if the sum of the difference of /R/ character’s LMFC count in the earliest arrival lane to the latest arrival lane, and the number of LMFC count up to the release of RBD elastic buffer exceeds the RBD elastic buffer size. If this is the root cause of lane deskew error, setting RBD offset is one of the techniques to overcome this issue. Not every RBD offset value is legal. Figure below illustrates the technique to decide the legal RBD offset value.

Figure 29. Selecting Legal RBD Offset Value

Because the IP core does not report the position of the earliest lane arrival with respect to the LMFC boundary, you must perform multiple power cycles to observe the RBD count and tune the RBD offset accordingly until no lane deskew error occurs. From the example in the figure above, the recommended RBD offset value is 4 or 5. Setting RBD offset to 1, 2 or 3 is illegal because this exceeds the RBD elastic buffer size for the F and K configurations.

Related Information
Level Two Title