JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/05/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

6.7. Debugging JESD204B Link Using System Console

The system console provides access to the JESD204B IP register sets through the Avalon® memory-mapped interfaces.

To use the system console, your design must contain a Platform Designer subsystem with the JTAG-to-Avalon-MM Master bridge or Nios® II Processor component. Connect the JESD204B IP Avalon® memory-mapped interface to the Avalon® memory-mapped master through the Platform Designer interconnect directly if the IP resides in the Platform Designer subsystem. Otherwise, connect the Avalon® memory-mapped interface through the Merlin slave translator if the IP is not part of the Platform Designer subsystem.

PHY Layer for All Devices Except Intel® Stratix® 10 E-tile Devices

Verify the PHY status through these signals in the <ip_variant_name> .v:

Table 90.  PHY Status Signals for All Supported Devices Except Intel® Stratix® 10 E-tile Devices
Design Signals
RX
  • rx_is_lockedtodata
  • rx_analogreset
  • rx_digitalreset
  • rx_cal_busy
TX
  • pll_locked
  • pll_powerdown
  • tx_analogreset
  • tx_digitalreset
  • tx_cal_busy
RX and TX (Duplex)
  • rx_is_lockedtodata
  • rx_analogreset
  • rx_digitalreset
  • rx_cal_busy
  • rx_seriallpbken
  • pll_locked
  • pll_powerdown
  • tx_analogreset
  • tx_digitalreset
  • tx_cal_busy

Use the rxphy_clk[0] or txphy_clk[0] signal as sampling clock for the Signal Tap Logic Analyzer.

For a normal operation of the JESD204B RX path, the rx_is_lockedtodata bit for each lane should be "1" while the rx_cal_busy, rx_analogreset, and rx_digitalreset bit for each lane should be "0".

For a normal operation of the JESD204B TX path, the pll_locked bit for each lane should be "1" while the tx_cal_busy, pll_powerdown, tx_analogreset, and tx_digitalreset bit for each lane should be "0".

Measure the rxphy_clk or txphy_clk frequency by connecting the clock to the CLKOUT pin on the FPGA. The frequency should be the same as link clock frequency for PCS option in Hard PCS or Soft PCS mode. The frequency is half of the link clock frequency for PCS option in PMA Direct mode.

PHY Layer for Intel® Stratix® 10 E-tile Devices

Verify the PHY status through these signals in the <ip_variant_name> .v:

Table 91.  PHY Status Signals for Intel® Stratix® 10 E-tile Devices
Design Signals
RX
  • rx_is_lockedtodata
  • phy_rx_ready
  • phy_rx_pma_ready
TX
  • phy_tx_ready
  • phy_tx_pma_ready
Use the rxphy_clk[0] or txphy_clk[0] signal as the acquisition clock. Then add the following set_false_path constraint in the SDC script. 
set_false_path -from 
<instance_name>|inst_phy|inst_xcvr|*counter_*x_ready|r_reset -to 
auto_fab*sld_signaltap_inst*

For a normal operation of the JESD204B RX path, the phy_rx_pma_ready, phy_rx_ready and the rx_islockedtodata bits for each lane should be "1".

For a normal operation of the JESD204B TX path, the phy_tx_pma_ready and phy_tx_ready bits for each lane should be "1".

Measure the rxphy_clk or txphy_clk frequency by connecting the clock to the CLKOUT pin on the FPGA. The frequency should be the same as link clock frequency.

Link Layer

Verify the RX and TX PHY-link layer interface operation through these signals in the <ip_variant_name> _inst_phy.v:

Table 92.  RX and TX PHY-Link Layer Signals
Design Signals
RX
  • jesd204_rx_pcs_data
  • jesd204_rx_pcs_data_valid
  • jesd204_rx_pcs_kchar_data
  • jesd204_rx_pcs_errdetect
  • jesd204_rx_pcs_disperr
TX
  • jesd204_tx_pcs_data
  • jesd204_tx_pcs_kchar_data

Verify the link layer operation through these signals in the <ip_variant_name> .v:

Table 93.  RX and TX Link Layer Signals
Design Signals
RX
  • jesd204_rx_avs_rst_n
  • rxlink_rst_n_reset_n
  • rx_sysref (for Subclass 1 only)
  • rx_dev_sync_n
  • jesd204_rx_int
  • alldev_lane_aligned
  • dev_lane_aligned
  • rx_somf

Use the rxlink_clk signal as the sampling clock.

TX
  • jesd204_tx_avs_rst_n
  • txlink_rst_n_reset_n
  • tx_sysref (for Subclass 1 only)
  • sync_n
  • tx_dev_sync_n
  • mdev_sync_n
  • jesd204_tx_int

Intel® recommends that you verify the JESD204B functionality by accessing the DAC SPI registers or any debug feature provided by the DAC manufacturer.

Figure 34. JESD204B Link InitializationThis is a Signal Tap image during the JESD204B link initialization. The JESD204B link has two transceiver channels (L = 2).


Description of the timing diagram:

  • a. The JESD204B link is out of reset.
  • b. The RX CDR is locked and PCS outputs valid characters to link layer.
  • c. No running disparity error and 8B/10B block within PCS successfully decodes the incoming characters.
  • d. The ADC transmits /K/ character or BC hexadecimal number to the FPGA, which starts the CGS phase.
  • e. Upon receiving 4 consecutive /K/ characters, the link layer deasserts the rx_dev_sync_n signal.
  • f. The JESD204B link transition from CGS to ILAS phase when ADC transmit /R/ or 1C hexadecimal after /K/ character.
  • g. Start of 2nd multiframe in ILAS phase. 2nd multiframe contains the JESD204B link configuration data.
  • h. Start of 3rd multiframe.
  • i. Start of 4th multiframe.
  • j. Device lanes alignment is achieved. In this example, there is only one device, the dev_lane_aligned connects to alldev_lane_aligned and both signals are asserted together.
  • k. Start of user data phase where user data is streamed through the JESD204B link.

Transport Layer

Verify the RX transport layer operation using these signals in the altera_jesd204_transport_rx_top.sv:

  • jesd204_rx_dataout
  • jesd204_rx_data_valid
  • jesd204_rx_data_ready
  • jesd204_rx_link_data_ready
  • jesd204_rx_link_error
  • rxframe_rst_n

Use the rxframe_clk signal as the sampling clock.

For normal operation, the jesd204_rx_data_valid, jesd204_rx_data_ready, and jesd204_rx_link_data_ready signals should be asserted while the jesd204_rx_link_error should be deasserted. You can view the ramp or sine wave test pattern on the jesd204_rx_dataout bus.

Figure 35. Ramp Pattern on the jesd204_rx_dataout Bus This is a Signal Tap II image during the JESD204B user data phase with ramp pattern transmitted from the ADC.


Verify the TX transport layer operation using these signals in the altera_jesd204_transport_tx_top.sv:

  • txframe_rst_n
  • jesd204_tx_datain
  • jesd204_tx_data_valid
  • jesd204_tx_data_ready
  • jesd204_tx_link_early_ready
  • jesd204_tx_link_data_valid
  • jesd204_tx_link_error

Use the txframe_clk signal as the sampling clock.

For normal operation, the jesd204_tx_data_valid, jesd204_tx_data_ready, jesd204_tx_link_early_ready, and jesd204_tx_link_data_valid signals should be asserted while the jesd204_tx_link_error should be deasserted. You can verify the user data arrangement (shown in the data mapping tables in the TX Path Data Remapping section in the Design Examples for JESD204B IP Core User Guide) by referring to the jesd204_tx_datain bus.

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