JESD204B Intel® FPGA IP User Guide

Download PDF
ID 683442
Date 5/05/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

5.3. Programmable LMFC Offset

If your JESD204B subsystem design has deterministic latency issue, the programmable LMFC offset in the TX and RX IP cores provides flexibility to ensure that deterministic latency can be achieved.

The TX LMFC offset can align the TX LMFC counter to the LMFC counter in DAC; the RX LMFC offset can align the RX LMFC counter to the LMFC counter in ADC. Phase offset between the TX and RX LMFC counters in the both ends of the JESD204B link contributes to deterministic latency uncertainty. The phase offset is caused by:

  • SYSREF trace length mismatch in the PCB between the TX and RX devices (FPGA and converters).
  • delay differences in resetting the LMFC counter when SYSREF pulses are detected by the FPGA and converter devices.

The RX device in the JESD204B link is responsible for deterministic latency adjustments. The following figure illustrates the adjustments that you can make to the RX LMFC offset using the csr_lmfc_offset field in the syncn_sysref_ctrl register. This is an alternative to using csr_rbd_offset to achieve deterministic latency.

Figure 30. Selecting Legal LMFC Offset Value for RX

Sequence of events in the diagram:

  1. Due to trace length mismatch, SYSREF pulse arrives at the ADC first.
  2. Some deterministic delay occurs in between the time when the SYSREF pulse is sampled high to the reset of the ADC internal LMFC counter.
  3. The SYSREF pulse arrives at the FPGA IP core port, rx_sysref, after the pulse's arrival at the ADC.
  4. The FPGA IP core's internal LMFC counter resets two link clock cycles after SYSREF is sampled.
  5. The LMFC phase offset between the LMFC counter at ADC and FPGA is ~3.5 link clock cycles.
  6. The FPGA deasserts SYNC_N at the LMFC boundary.
  7. The ADC JESD204B core detects the SYNC_N deassertion.
  8. Because SYNC_N deassertion is detected after the second LMFC boundary at ADC, ILAS transmission begins at the third LMFC boundary.
  9. In this example, the ILAS arrives at the IP core's RBD elastic buffer within one local multiframe. In other system, the arrival at the RBD elastic buffer can span more than one local multiframe. Assuming csr_rbd_offset = 0, RBD elastic buffer may be released at the third or fourth LMFC boundary due to power cycle variation.
  10. Setting csr_lmfc_offset = 5 resets the LMFC counter to the value of 5.
  11. The first LMFC boundary is delayed by three link clock cycles.
  12. The third LMFC boundary has been delayed past the latest arrival lane power cycle variation. The RBD elastic buffer is always released at the third LMFC boundary.

You should set a safe LMFC offset value to ensure deterministic latency from one power cycle to another power cycle. In Figure 31, the illegal csr_lmfc_offset values of 1, 2, and 3 causes lane de-skew error because the RBD buffer size has exceeded.

Figure 31. Selecting Illegal LMFC Offset Value for RX, Causing Lane Deskew Error

You can use the TX LMFC offset to align the LMFC counter in IP core to the LMFC counter in DAC.

Figure 32. Example of Reducing LMFC Phase Offset between TX and RX LMFC Counter

Sequence of events in the diagram:

  1. SYSREF pulse arrives at the FPGA IP core port, tx_sysref.
  2. The IP core's internal LMFC counter resets after two link clock cycles.
  3. SYSREF pulse is sampled by the DAC.
  4. The DAC's internal LMFC counter resets after a deterministic delay.
  5. The LMFC phase offset is ~3.5 link clock cycles.
  6. The DAC deasserts SYNC_N at the LMFC boundary.
  7. SYNC_N deassertion is detected by the JESD204B IP core.
  8. Because SYNC_N deassertion is detected after the second LMFC boundary at the FPGA, ILAS transmission begins at the third LMFC boundary.
  9. The csr_lmfc_offset is set to 4. This delays the TX LMFC boundary by 4 link clock cycles. If csr_lmfc_offset is set to 5, the TX LMFC boundary is delayed by 3 link clock cycles.
  10. The LMFC phase offset between the TX and RX LMFC reduces to 0.5 link clock cycle.

Alternative to tuning RBD offset at the DAC, adjusting TX LMFC offset in the FPGA helps you to achieve deterministic latency. You should perform multiple power cycles and read the RBD counts at the DAC to determine whether deterministic latency is achieved and RBD elastic buffer size has not exceeded.

The SYSREF pipeline registers in the FPGA introduce additional latency to SYSREF when detected by the IP core. Therefore, you can use TX LMFC offset to reduce or eliminate this additional latency. The next figure illustrates the technique of optimizing latency using TX LMFC offset.

Figure 33. Optimizing IP Core Latency Using TX LMFC Offset

Sequence of events in the diagram:

  1. The DAC samples the SYSREF pulse.
  2. The DAC's internal LMFC counter resets after a deterministic delay.
  3. The SYSREF pipeline registers introduces an additional 2 link clock latency.
  4. The csr_lmfc_offset field is set to 4. The IP core internal LMFC counter resets after 2 link clock cycles.
  5. The LMFC boundary is delayed by 4 link clock.
  6. The DAC deasserts SYNC_N at the LMFC boundary.
  7. SYNC_N deassertion is detected by the JESD204B IP core.
  8. Because LMFC boundary is delayed by 4 link clock, the IP core detects the SYNC_N deassertion before the second LMFC boundary. ILAS transmission begins at the second LMFC boundary instead of the third LMFC boundary (in Figure 32). The latency is shortened by 4 LMFC counts or link clock cycles.

The csr_lmfc_offset field provides a convenient way to achieve deterministic latency and potentially optimizing the IP core latency. There are other ways that you can achieve deterministic latency by using the features available at the converters. Consult the converter manufacturer for details of these features.

Level Two Title