AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

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ID 683437
Date 12/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Restrictions 3. Enabling I/O Release 4. Debugging Early I/O Release A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release
1. Introduction x
1.1. Early I/O Release Use Cases 1.2. Early I/O Release Flow
2. Design Restrictions x
2.1. Peripheral and Core RBF are a Matched Pair 2.2. EMIF Pin Usage Restrictions
3. Enabling I/O Release x
3.1. Intel® Quartus® Prime Project Settings 3.2. Platform Designer Component Settings 3.3. Creating Split RBF Images 3.4. Configuring U-Boot to use Split RBF Files
1. Introduction
2. Design Restrictions
3. Enabling I/O Release
4. Debugging Early I/O Release
A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release

3.1. Intel® Quartus® Prime Project Settings

Follow the steps below

  1. Enabling Early I/O Release in the Intel® Quartus® Prime project settings requires you to check one checkbox. To access the checkbox option, select the Assignments > Device drop down menu item.
  2. Click the Device and Pin Options box in the dialog window.
  3. Once the Device and Pin Options dialog window is available, scroll the Options list to the bottom to find the Enables the HPS early release of HPS IO option and ensure that it is checked.
  4. Selecting this option commands the FPGA compilation tools to set the Early I/O Release option bit in the assembled configuration stream.
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