AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

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ID 683437
Date 12/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Restrictions 3. Enabling I/O Release 4. Debugging Early I/O Release A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release
1. Introduction x
1.1. Early I/O Release Use Cases 1.2. Early I/O Release Flow
2. Design Restrictions x
2.1. Peripheral and Core RBF are a Matched Pair 2.2. EMIF Pin Usage Restrictions
3. Enabling I/O Release x
3.1. Intel® Quartus® Prime Project Settings 3.2. Platform Designer Component Settings 3.3. Creating Split RBF Images 3.4. Configuring U-Boot to use Split RBF Files
1. Introduction
2. Design Restrictions
3. Enabling I/O Release
4. Debugging Early I/O Release
A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release

1.2. Early I/O Release Flow

When using Early I/O release as part of the FPGA design compilation process, two Raw Binary Format (.rbf) configuration files are generated: a peripheral .rbf file and a core .rbf file. Together, these configuration files contain the same data as a combined configuration .rbf file that is generated when the Early I/O Release feature is not used.

The peripheral .rbf file is loaded first and configures the FPGA I/O, Shared I/O and HPS EMIF. The core .rbf is loaded next and completes the FPGA configuration sequence by configuring the FPGA fabric.

After the peripheral .rbf is successfully loaded, the Intel® Arria® 10 SoC FPGA HPS EMIF pins are released and the interface begins calibration.

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