AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

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ID 683437
Date 12/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Restrictions 3. Enabling I/O Release 4. Debugging Early I/O Release A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release
1. Introduction x
1.1. Early I/O Release Use Cases 1.2. Early I/O Release Flow
2. Design Restrictions x
2.1. Peripheral and Core RBF are a Matched Pair 2.2. EMIF Pin Usage Restrictions
3. Enabling I/O Release x
3.1. Intel® Quartus® Prime Project Settings 3.2. Platform Designer Component Settings 3.3. Creating Split RBF Images 3.4. Configuring U-Boot to use Split RBF Files
1. Introduction
2. Design Restrictions
3. Enabling I/O Release
4. Debugging Early I/O Release
A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release

3.3. Creating Split RBF Images

After the Intel® Quartus® Prime FPGA project has been successfully compiled and a .sof configuration file has been generated, a pair of split .rbf files must be generated using the quartus_cpf command line utility. Use the -c option to indicate that this is a conversion step, and use the --hps option to indicate that the .rbf should be split into peripheral and core files. The remaining arguments are the input .sof file and the output .rbf file base name. 

$ quartus_cpf --convert --hps -o bitstream_compression=on 
output_files/ghrd_10as066n2.sof output_files/ghrd_10as066n2.rbf
Info: *******************************************************************
Info: Running Quartus Prime Convert_programming_file
    Info: Version 18.0.1 Build 261 06/28/2018 SJ Pro Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sun Jul 15 23:05:21 2018
Info: Command: quartus_cpf --convert --hps -o bitstream_compression=on output_files/ghrd_10as066n2.sof output_files/ghrd_10as066n2.rbf
Info: Quartus Prime Convert_programming_file was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 1297 megabytes
    Info: Processing ended: Sun Jul 15 23:05:45 2018
    Info: Elapsed time: 00:00:24
    Info: Total CPU time (on all processors): 00:00:58
$ ls output_files/*.rbf
output_files/ghrd_10as066n2.core.rbf  output_files/ghrd_10as066n2.periph.rbf

The command example listed above results in two new generated files: ghrd_10as066n2.core.rbf and ghrd_10as066n2.periph.rbf. These are the split .rbf files. The ghrd_10as066n2.periph.rbf must be loaded first, followed by the ghrd_10as066n2.core.rbf file.

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