AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release

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ID 683437
Date 12/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Restrictions 3. Enabling I/O Release 4. Debugging Early I/O Release A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release
1. Introduction x
1.1. Early I/O Release Use Cases 1.2. Early I/O Release Flow
2. Design Restrictions x
2.1. Peripheral and Core RBF are a Matched Pair 2.2. EMIF Pin Usage Restrictions
3. Enabling I/O Release x
3.1. Intel® Quartus® Prime Project Settings 3.2. Platform Designer Component Settings 3.3. Creating Split RBF Images 3.4. Configuring U-Boot to use Split RBF Files
1. Introduction
2. Design Restrictions
3. Enabling I/O Release
4. Debugging Early I/O Release
A. Document Revision History for Using Intel® Arria® 10 SoC FPGA Early I/O Release

3.2. Platform Designer Component Settings

Early I/O Release is enabled by setting an option in the Intel® Arria® 10 HPS EMIF component. This option is set using the Platform Designer design tool.

Open the Parameters window for the Intel® Arria® 10 HPS EMIF component and ensure that the Enable HPS Early Release Mode option in the General tab is checked.

Selecting this option parameter in the Intel® Arria® 10 HPS EMIF disables the component reset signal from the FPGA core logic. Setting this option is important to ensure that the EMIF does not accidentally reset when loading the FPGA core image.

When not using the Early I/O Release feature, the Intel® Arria® 10 HPS EMIF component is held in reset until the FPGA core is fully configured. However, when using the Early I/O Release feature, the EMIF is released from reset before the FPGA core is configured. This option disables any connection from the FPGA core logic to the EMIF reset.

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