Intel FPGA Programmable Acceleration Card N3000-N Data Sheet

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ID 683434
Date 12/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. Intel® Provided FPGA Image A. References B. Safety and Regulatory Information C. Document Revision History for the Intel FPGA Programmable Acceleration Card N3000-N Data Sheet
2. Overview x
2.1. Intel® FPGA PAC N3000-N Block Diagram 2.2. Overview of Product Features 2.3. PCIe Overview 2.4. Board Management Controller Overview
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GT FPGA 2.2.2. Intel® Ethernet Controller XL710-BM2 Network Interface Controller 2.2.3. On-Board Memory 2.2.4. Software and Firmware 2.2.5. Power 2.2.6. Network Interface
2.2.6. Network Interface x
2.2.6.1. Intel® Ethernet Connection C827 Retimer
2.4. Board Management Controller Overview x
BMC Features Sensor Monitoring Features 2.4.1. Field Replaceable Unit Identification (FRUID) EEPROM
5. Thermal Specifications x
5.1. Cooling Requirements
B. Safety and Regulatory Information x
B.1. Regulatory Compliance
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. Intel® Provided FPGA Image
A. References
B. Safety and Regulatory Information
C. Document Revision History for the Intel FPGA Programmable Acceleration Card N3000-N Data Sheet

2.4. Board Management Controller Overview

The Intel® FPGA PAC N3000-N contains an Intel® MAX® 10 Board Management Controller (BMC). This BMC is responsible for controlling, monitoring and giving low-level access to board features. The Intel® MAX® 10 BMC interfaces with on-board sensors, the FPGA and the flash, and controls power-on/power-off sequences, FPGA configuration and telemetry data polling. The BMC communicates with the server system controller using either Platform Level Data Model (PLDM) version 1.1.1 protocol or I2C through the PCIe* SMBus.

An external Quad SPI flash stores the BMC firmware and the BMC firmware for the Nios® II is field upgradeable over the PCIe* using the remote system update feature. Only Intel® provided BMC firmware is permitted.

BMC Features

  • Supports FPGA configuration and reconfiguration.
  • Supports Secure Remote System Update for Intel® MAX® 10 BMC FPGA update image, Intel® Arria® 10 GT FPGA user image, and Nios® firmware image.
  • Monitors telemetry data for board temperature, voltage, and current.
  • Reports telemetry data to host BMC through Platform Level Data Model (PLDM) over Management Component Transport Protocol (MCTP) SMBus.
  • Provides protective action when temperature and auxiliary power readings are outside of critical thresholds.
  • Provides power up/down sequencing and fault detection with automatic shut-down protection.
  • Interfaces with sensors, FPGA, flash, and QSFPs.

Sensor Monitoring Features

The Intel® FPGA PAC N3000-N incorporates sensor monitoring that allow the host server to read telemetry data such as voltage, current, power, and temperature information from various components on the board. The host system controller accesses these sensors using either PLDM over MCTP or I2C through the PCIe* SMBus.
Table 3.  PDRs Sensor Names and Record Handle
Function Sensor Name Sensor Information PLDM
Sensor Reading Source (Component) PDR Record Handle Thresholds in PDR Threshold changes allowed through PLDM
Total Intel® FPGA PAC input power Board Power Calculate from PCIe fingers 12V Current and Voltage 1 0 No
PCIe* fingers 12 V Current 12 V Backplane Current PAC1932 SENSE1 2 0 No
PCIe* fingers 12 V Voltage 12 V Backplane Voltage PAC1932 SENSE1 3 0 No
1.2 V Rail Voltage 1.2 V Voltage MAX10 ADC 4 0 No
1.8 V Rail Voltage 1.8 V Voltage MAX 10 ADC 6 0 No
3.3 V Rail Voltage 3.3 V Voltage MAX 10 ADC 8 0 No
FPGA Core Voltage FPGA Core Voltage LTC3884 (U44) 10 0 No
FPGA Core Current FPGA Core Current LTC3884 (U44) 11 0 No
FPGA Core Temperature FPGA Core Temperature FPGA temp diode through TMP411 12

Upper Warning: 90

Upper Fatal: 100

 Yes
Board Temperature Board Temperature TMP411 (U65) 13

Upper Warning: 85

Upper Fatal: 100 		Yes
QSFP A Voltage QSFP A Voltage

External QSFP module (J4)

 14 0 No
QSFP A Temperature QSFP A Temperature

External QSFP module (J4)

 15

Upper Warning: Value set by QSFP Vendor

Upper Fatal: Value set by QSFP Vendor

 No
PCIe Auxiliary 12V Current 12 V AUX PAC1932 SENSE2 24 0 No
PCIe Auxiliary 12V Voltage 12 V AUX Voltage PAC1932 SENSE2 25 0 No
QSFP B Voltage QSFP B Voltage External QSFP module (J5) 37 0 No
QSFP B Temperature QSFP B Temperature External QSFP module (J5) 38

Upper Warning: Value set by QSFP Vendor

Upper Fatal: Value set by QSFP Vendor

 No
Intel® C827) Retimer A Core Temperature Retimer A Core Temperature Intel® C827) Retimer chip (88EC055) (U18A) 44 0 No
Intel® C827) Retimer A Serdes Temperature Retimer A Serdes Temperature Intel® C827) Retimer chip (88EC055) (U18A) 45 0 No
Intel® C827) Retimer B Core Temperature Retimer B Core Temperature Intel® C827) Retimer chip (88EC055) (U23A) 46 0 No
Intel® C827) Retimer B Serdes Temperature Retimer B Serdes Temperature Intel® C827) Retimer chip (88EC055) (U23A) 47 0 No

Refer to the Board Monitoring through I2C SMBus section of the Board Management Controller User Guide: Intel FPGA Programmable Acceleration Card N3000-N for information on telemetry data register map.

The BMC shuts down power to the board under the following conditions:
  • 12 V Auxiliary or 12 V backplane supply voltage is below 10.46 V
  • FPGA core temperature reaches 100 °C
  • Board temperature reaches 100 °C
Note: All faceplate LEDs blink yellow to indicate a card has shutdown due to one of the above conditions.
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