Visible to Intel only — GUID: qna1510793199536
Ixiasoft
Visible to Intel only — GUID: qna1510793199536
Ixiasoft
5. Reset
Asserting the external hard reset i_csr_rst_n or the soft reset eio_sys_rst returns all Ethernet registers to their original values, including the statistics counters. It also returns all transceiver registers to their original values. An additional dedicated reset signal, i_reconfig_reset, resets the transceiver reconfiguration and Ethernet reconfiguration interfaces.
The general reset signals reset the following functions:
- soft_tx_rst, i_tx_rst_n: Resets the TX PCS and TX MAC. This reset leads to deassertion of the o_tx_lanes_stable output signal.
- soft_rx_rst, i_rx_rst_n: Resets the RX PCS and RX MAC. This reset leads to deassertion of the o_rx_pcs_ready output signal.
- eio_sys_rst, i_csr_rst_n: Resets the IP core. Resets the TX and RX MACs, Ethernet reconfiguration registers, PCS, and transceivers. This reset leads to deassertion of the o_tx_lanes_stable and o_rx_pcs_ready output signals. Use this signal to reset the IP core whenever the transceiver is recalibrated.
Reset Signal | Block | |||||||
---|---|---|---|---|---|---|---|---|
MAC TX Datapath | PCS TX Datapath | MAC RX Datapath | PCS RX Datapath | PHY | CSRs (MAC/PHY) | TX Statistics | RX Statistics | |
i_csr_rst_n, eio_sys_rst | √ |
√ |
√ |
√ |
√ |
√ |
√ |
√ |
i_tx_rst_n, soft_tx_rst |
√ |
√ |
X |
X |
X |
X |
X |
X |
i_rx_rst_n, soft_rx_rst |
X |
X |
√ |
√ |
X |
X |
X |
X |
soft_clear_tx_stats |
X |
X |
X |
X |
X |
X |
√ |
X |
soft_clear_rx_stats |
X |
X |
X |
X |
X |
X |
X |
√ |
In addition, the synchronous i_reconfig_reset signal resets the IP core transceiver reconfiguration interface and the Ethernet reconfiguration interface. Associated clock is the i_reconfig_clk, which clocks the two interfaces.
System Considerations
- You should perform a system reset before beginning IP core operation by asserting and deasserting i_csr_rst_n and i_reconfig_reset signals together. To assert both signals, set i_csr_rst_n signal to 0 and i_reconfig_reset signal to 1. To deassert both signals, set i_csr_rst_n to 1 and i_reconfig_reset to 0. The IP core implements the correct reset sequence to reset the entire IP core.
-
If you assert the transmit reset when the downstream receiver is already aligned, the receiver loses alignment. Before the downstream receiver loses lock, it might receive some malformed frames.
-
If you assert the receive reset while the upstream transmitter is sending packets, the packets in transit are corrupted.
-
If the ATX PLL loses lock, the IP core forces a transmit side and a receive side reset. To ensure the IP core also resets the Hard IP for Ethernet, you must assert the i_csr_rst_n signal after the ATX PLL loses lock.
-
If the IP core suffers loss of signal on the serial links, it asserts the receive reset.
- While the eio_sys_rst reset is asserted, do not access any other registers.
- If the auto-negotiation and link training (AN/LT) are enabled, do not use eio_sys_rst reset until AN/LT operation is complete. In the data mode, you can use eio_sys_rst reset as long as no other Avalon-MM access is in progress.
The following diagrams show the reset sequences for TX and RX datapaths when you assert i_tx_rst_n and i_rx_rst_n reset signals.