3.1. Parameter Editor Parameters

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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3.1. Parameter Editor Parameters

The H-Tile Hard IP for Ethernet parameter editor provides the parameters you can set to configure your H-Tile Hard IP for Ethernet IP core variation and simulation and hardware design examples.

The H-Tile Hard IP for Ethernet parameter has two tabs, an IP tab and an Example Design tab. For information about the Example Design tab, refer to the H-Tile Hard IP for Ethernet Stratix® 10 FPGA IP Design Example User Guide .

Table 9. H-Tile Hard IP for Ethernet Parameters: IP TabThis table does not provide information about invalid parameter value combinations. If you make selections that create a conflict, the parameter editor generates error messages in the System Messages pane.
Parameter	Range	Default Setting	Parameter Description
General Options
Ethernet Rate	100G	100G	Selects the IP core Ethernet data rate.
Ethernet IP layers	MAC+PCS PCS Only OTN FlexE	MAC+PCS	Selects the type of Ethernet layer in your IP core variation. MAC+PCS: Full Ethernet MAC and PCS PCS Only: Ethernet PHY with MII interface OTN: Ethernet PHY suitable for an OTN Ethernet PHY (PCS without 64/66B encoding/decoding and scrambling/de-scrambling). Note: The H-Tile Hard IP for Ethernet IP provides preliminary support for the OTN feature. For further inquiries, contact your nearest Intel sales representative or file an Intel Premier Support (IPS) case and quote ID #22019851155. FlexE: Ethernet PHY suitable for Flex Ethernet PHY (PCS without 64/66B encoding/decoding).
Ready Latency	0–3	0	Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® -ST interface property that defines the number of clock cycles of delay from when the IP core asserts the `o_tx_ready` signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications. In PCS Only, OTN, and FlexE variations, this parameter has no effect. Selecting a longer latency (higher number) eases timing closure at the expense of increased latency for the TX datapath in MAC+PCS variations.
MAC Options: Basic Tab Note: In PCS Only variations, these parameters have no effect.
TX maximum frame size	65–65535	1518	Maximum packet size (in bytes) the IP core can transmit on the Ethernet link without reporting an oversized packet in the TX statistics counters. MAC+PCS variations support the entire range. In PCS Only, OTN, and FlexE variations, this parameter has no effect and remains at the default value of 1518.
RX maximum frame size	65–65535	1518	Maximum packet size (in bytes) the IP core can receive on the Ethernet link without reporting an oversized packet in the RX statistics counters. If you turn on the Enforce maximum frame size parameter, the IP core truncates incoming Ethernet packets that exceed this size. MAC+PCS variations support the entire range. In PCS Only, OTN, and FlexE variations, this parameter has no effect and remains at the default value of 1518.
Enforce maximum frame size	True False	False	Specifies whether the IP core is able to receive an oversized packet or truncates these packets.
Link fault generation option	OFF Unidirectional Bidirectional	OFF	Specifies the IP core response to link fault events. Bidirectional link fault handling complies with the Ethernet specification, specifically IEEE 802.3 Figure 81-11. Unidirectional link fault handling implements IEEE 802.3 Clause 66: in response to local faults, the IP core transmits Remote Fault ordered sets in interpacket gaps but does not respond to incoming Remote Fault ordered sets. The OFF option is provided for backward compatibility.
Stop TX traffic when link partner sends pause	Yes No Disable Flow Control	No	Selects whether the IP core responds to PAUSE frames from the Ethernet link by stopping TX traffic, or not. This parameter has no effect if flow control is disabled. If you disable flow control, the IP core neither responds to incoming PAUSE and PFC frames nor generates outgoing PAUSE and PFC frames. If this parameter has the value of No, you can use the `i_tx_pause` signal on the TX client interface to force the TX MAC to stop TX traffic. Flow control is not supported for PCS, OTN or FlexE only variations. Choose Disable Flow Control option when using PCS, OTN or FlexE only variations.
Bytes to remove from RX frames	None Remove CRC bytes Remove CRC and PAD bytes	Remove CRC bytes	Selects whether the RX MAC should remove CRC bytes, or remove CRC and PAD bytes, or do not remove anything from incoming RX frames before passing them to the RX MAC Client. If the PAD bytes and CRC are not needed downstream, this option can reduce the need for downstream packet processing logic
Forward RX pause requests	True False	False	Selects whether the RX MAC forwards incoming PAUSE and PFC frames on the RX client interface, or drops them after internal processing. Note: If flow control is turned off, the IP core forwards all incoming PAUSE and PFC frames directly to the RX client interface and performs no internal processing. In that case this parameter has no effect.
Use source address insertion	True False	False	Selects whether the IP core supports overwriting the source address in an outgoing Ethernet packet with the value in the `TXMAC_SADDR` registers at offsets 0x40C and 0x40D. If the parameter is turned on, the IP core overwrites the packet source address from the register if `i_tx_skip_crc` has the value of 0. If the parameter is turned off, the IP core does not overwrite the source address. Source address insertion applies to PAUSE and PFC packets provided on the TX MAC client interface, but does not apply to PAUSE and PFC packets the IP core transmits in response to the assertion of `i_tx_pause` or `i_tx_pfc[n]` on the TX MAC client interface.
TX MAC source address	0–(2⁴⁸–1)	0x00_11_22_33_44_55	Source address with which the IP core initializes the `TXMAC_SADDR` registers at offsets 0x40C and 0x40D. Note: In the Quartus® Prime Pro Edition software release v17.1, the default value displays in the parameter editor in decimal notation (as 7358829205), and if you modify the value, you must specify the new value in decimal notation. Note: In the Quartus® Prime Pro Edition software release v17.1, the parameter input field appears only when you turn on the Use source address insertion parameter, and the parameter name does not display. In future releases the parameter name will appear.
TX VLAN detection	True False	True	Specifies whether the IP core TX statistics block treats TX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the `TxFrameOctetsOK` counter at offsets 0x862 and 0x863. If turned on, the IP core identifies these frames in TX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
RX VLAN detection	True False	True	Specifies whether the IP core RX statistics block treats RX VLAN and Stacked VLAN Ethernet frames as regular control frames, or performs Length/Type field decoding, includes these frame in VLAN statistics, and counts the payload bytes instead of the full Ethernet frame in the `RxFrameOctetsOK` counter at offsets 0x962 and 0x963. If turned on, the IP core identifies these frames in RX statistics as VLAN or Stacked VLAN frames. If turned off, the IP core treats these frames as regular control frames.
MAC Options: Specialized Tab Note: In PCS, OTN, and FlexE Only variations, these parameters have no effect.
Enable preamble passthrough	True False	False	If turned on, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and SFD to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble to be sent in the Ethernet frame.
Enable strict preamble check	True False	False	If turned on, the IP core rejects RX packets whose preamble is not the standard Ethernet preamble (0x55_55_55_55_55_55). This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.
Enable strict SFD check	True False	False	If turned on, the IP core rejects RX packets whose SFD byte is not the standard Ethernet SFD (0xD5). This option provides an additional layer of protection against spurious Start frames that can occur at startup or when bit errors occur.
Average Inter-packet Gap	1 8 10 12	12	Specifies the average minimum inter-packet gap (IPG) the IP core maintains on the TX Ethernet link. The default value of 12 complies with the Ethernet standard. The remaining values support increased throughput. The value of 1 specifies that the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. The IP core no longer complies with the Ethernet standard, but the application has control over the average gap and maximizing the throughput. For more information, refer to the Inter-Packet Gap Generation and Insertion section.
Additional IPG removed per AM period	Integer	0	Specifies the number of inter-packet gaps the IP core removes per alignment marker period, in addition to the default number required for protocol compliance. In 100GBASE-R4 variations, the default number is 20. Each increment of 1 in the value of Additional IPG removed per AM period increases throughput by 3ppm in 100GBASE-R4 variations. To specify larger throughput increases, use the Average Inter-packet Gap parameter.
PMA Options
PHY Reference Frequency	644.53125 MHz 322.265625 MHz	644.53125 MHz	Sets the expected incoming PHY `i_clk_ref` reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100 ppm).
AN/LT Options
Enable AN/LT	True False	False	If this parameter is turned on, the IP core supports auto-negotiation as defined in IEEE Standard 802.3-2015 Clause 73 and link training as defined in IEEE Standard 802.3-2015 Clauses 92 and 93. If this parameter is turned off, the IP core does not support these features, and the other parameters on this tab are not available. Auto-negotiation and link training features are available only in MAC+PCS variation.
Status clock rate	100–162 MHz	100 MHz	Sets the expected incoming `i_reconfig_clk` frequency. The input clock frequency must match the frequency you specify for this parameter. The IP core is configured with this information to ensure the IP core measures the link fail inhibit time accurately (determines the value of the Link Fail Inhibit timer (IEEE 802.3 clause 73.10.2) correctly).
Auto-Negotiation
Enable Auto-Negotiation	True False	True	If this parameter is turned on, the IP core includes logic to implement auto-negotiation as defined in Clause 73 of IEEE Std 802.3–2015. If this parameter is turned off, the IP core does not include auto-negotiation logic and cannot perform auto-negotiation.
Link fail inhibit time	500–510 ms	504 ms	Specifies the time before link status is set to FAIL or OK. A link fails if the time duration specified by this parameter expires before link status is set to OK. For more information, refer to Clause 73 Auto-Negotiation for Backplane Ethernet in IEEE Standard 802.3–2015. The IP core asserts the `o_rx_pcs_ready` signal to indicate link status is OK.
Enable CR Technology Ability	True False	True	If this parameter is turned on, the IP core advertises CR capability by default. If this parameter is turned off, but auto-negotiation is turned on, the IP core advertises KR capability by default.
Auto-Negotiation Master	Lane 0 Lane 1 Lane 2 Lane 3	Lane 0	Selects the master channel for auto-negotiation. The IP core does not provide a mechanism to change the master channel dynamically. The value you set in the parameter editor cannot be changed during operation.
Pause ability–C0	True False	True	If this parameter is turned on, the IP core indicates on the Ethernet link that it supports symmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.
Pause ability–C1	True False	True	If this parameter is turned on, the IP core indicates on the Ethernet link that it supports asymmetric pauses as defined in Annex 28B of Section 2 of IEEE Std 802.3–2015.
Link Training
Enable Link Training	True False	True	If this parameter is turned on, the IP core includes the link training module, which configures the remote link partner TX PMD for the lowest Bit Error Rate (BER). LT is defined in Clause 92 of IEEE Std 802.3–2015.
Number of frames to send at end of training	127 255	127	Specifies the number of additional training frames the local link partner delivers after training is complete to ensure that the link partner can correctly detect the local receiver state.
Enable Clause 72 PRBS11 generation	True False	False	If turned on, the IP core includes logic to generate the legacy Clause 72 PRBS pattern, in addition to the 25G Link Training patterns specified in Clause 92 of the IEEE Std 802.3–2015. If turned off, the IP core generates only the 25G Link Training patterns specified in Clause 92 of the IEEE Std 802.3–2015.
Link Training: PMA Parameters
VMAXRULE	0–31	30	Specifies the maximum V_OD. The default value, 30, represents 1200 mV. This default value is the maximum value the device should drive.
VMINRULE	0–31	6	Specifies the minimum V_OD. The default value, 6, represents 165 mV. This default value is the minimum value the device should drive.
VODMINRULE	0–31	14	Specifies the minimum V_OD for the first tap. The default value, 14, represents 440 mV.
VPOSTRULE	0–25	25	Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum post-tap setting.
VPRERULE	0–16	16	Specifies the maximum value that the internal algorithm for pre-emphasis will ever test in determining the optimum pre-tap setting.
PREMAINVAL	0–31	30	Specifies the Preset V_OD value. This value is set by the Preset command of the link training protocol, defined in Clause 72.6.10.2.3.1 of IEEE Std 802.3–2015.
PREPOSTVAL	0–25	0	Specifies the preset Post-tap value.
PREPREVAL	0–16	0	Specifies the preset Pre-tap value.
INITMAINVAL	0–31	25	Specifies the initial V_OD value. This value is set by the Initialize command of the link training protocol, defined in Clause 72.6.10.2.3.2 of IEEE Std 802.3–2015.
INITPOSTVAL	0–25	13	Specifies the initial Post-tap value.
INITPREVAL	0–16	3	Specifies the initial Pre-tap value.
Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint (NPDME)	True False	False	When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console.
Enable JTAG to Avalon Master Bridge	True False	False	Turn on this option to enable an internal JTAG connection to the Avalon-MM Master Bridge for register reconfigurations. This connection allows the System Console to run the Ethernet Link Inspector.

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

3.1. Parameter Editor Parameters