6.10. Miscellaneous Status and Debug Signals

H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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Date 5/03/2024

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6.10. Miscellaneous Status and Debug Signals

The H-Tile Hard IP for Ethernet IP core provides a handful of status and debug signals to support visibility into the actions of the IP core and the stability of IP core output clocks.

Table 23. Miscellaneous Status and Debug SignalsAll of the miscellaneous status and debug signals except the `i_stats_snapshot` signal are asynchronous.
Signal	Description
`o_cdr_lock`	Indicates that the recovered clocks are locked to data. The `o_clk_rec_div64` and `o_clk_rec_div66` clocks are reliable only after `o_cdr_lock` is asserted.
`o_tx_lanes_stable`	Asserted when all physical TX lanes are stable and ready to transmit data.
`o_rx_block_lock`	Asserted when the IP core completes 66-bit block boundary alignment on all PCS lanes.
`o_rx_am_lock`	Asserted when the RX PCS completes detection of alignment markers and deskew of the PCS lanes.
`o_rx_pcs_ready`	Asserted when the RX lanes are fully aligned and ready to receive data.
`o_local_fault_status`	Asserted when the RX MAC detects a local fault: the RX PCS detected a problem that prevents it from receiving data. This signal is functional only if you set the Choose Link Fault generation option parameter to the value of Bidirectional or Unidirectional in the parameter editor or if you overwrite the parameter editor parameter by setting the `link_fault_mode` RTL parameter to the value of `lf_bidir` or `lf_unidir`.
`o_remote_fault_status`	Asserted when the RX MAC detects a remote fault: the remote link partner sent remote fault order sets indicating that it is unable to receive data. This signal is functional only if you set the Choose Link Fault generation option parameter to the value of Bidirectional in the parameter editor or if you overwrite the parameter editor parameter by setting the `link_fault_mode` RTL parameter to the value of `lf_bidir`.
`i_stats_snapshot`	Directs the IP core to record a snapshot of the current state of the statistics registers. Assert this signal to perform the function of both the TX and RX statistics register shadow request fields at the same time, or to perform that function for multiple instances of the IP core simultaneously. Refer to TX Statistics Counters and RX Statistics Counters. Assert the signal for the desired duration of the freeze of read values in the statistics counters. The rising edge sets the `tx_shadow_on` field (bit [1]) of the `CNTR_TX_STATUS` register at offset 0x846 and the `rx_shadow_on` field (bit [1]) of the `CNTR_RX_STATUS` register at offset 0x946 to the value of 1 and the falling edge resets these bits. This signal is synchronous with the `i_clk_tx` clock.
`o_rx_hi_ber`	Asserted to indicate the RX PCS is in a HIBER state according to Figure 82-15 in the IEEE 802.3-2015 Standard. The IP core uses this signal in auto-negotiation and link training.
`o_ehip_ready`	The IP core deasserts this signal in response to an `i_csr_rst_n` or `i_tx_rst_n` reset, or either of the corresponding soft resets. After the reset process completes, the IP core reasserts this signal to indicate that the Hard IP for Ethernet block has completed initialization and is ready to interoperate with the main Stratix® 10 die. While the `o_ehip_ready` signal is low, the IP core datapath is not ready for data on the client interface nor ready for register accesses on the Ethernet reconfiguration interface.

Figure 33. Status Interface Behavior during Link Startup with Bidirectional Link Fault

Figure 34. Status Interface Behavior during Link Startup with Unidirectional or Link Fault Disable

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H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.10. Miscellaneous Status and Debug Signals