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1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. IP Core Generation Output ( Quartus® Prime Pro Edition)
2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor)
2.6. Simulating Intel® FPGA IP Cores
2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5.1. Register Map
5.2. Register Access Definition
5.3. Primary MAC Address
5.4. MAC Reset Control Register
5.5. TX Configuration and Status Registers
5.6. Flow Control Registers
5.7. Unidirectional Control Registers
5.8. RX Configuration and Status Registers
5.9. Timestamp Registers
5.10. ECC Registers
5.11. Statistics Registers
6.1. Clock and Reset Signals
6.2. Speed Selection Signal
6.3. Error Correction Signals
6.4. Unidirectional Signals
6.5. Avalon® Memory-Mapped Interface Programming Signals
6.6. Avalon® Streaming Data Interfaces
6.7. Avalon® Streaming Flow Control Signals
6.8. Avalon® Streaming Status Interface
6.9. PHY-side Interfaces
6.10. IEEE 1588v2 Interfaces
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6.2. Speed Selection Signal
Signal | Operating Mode | Direction | Width | Description |
---|---|---|---|---|
speed_sel | 10G, 1G/10G,10M/100M/1G/10G | In | 2 | Connect this asynchronous signal to the PHY to obtain the PHY's speed:
The speed_sel signal can be synchronized to TX or RX clock of the LL Ethernet 10G MAC Intel® FPGA IP core. Before the speed change, make sure the MAC TX and RX datapaths are idle with no packet transmission. After the line rate changes, trigger a reset on the TX and RX datapaths by asserting these active-low reset signals, tx_rst_n and rx_rst_n. |
1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G | In | 3 |