Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core

You customize the Intel® FPGA IP core by specifying the parameters on the parameter editor in the Quartus® Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 13.  Low Latency Ethernet 10G MAC Intel® FPGA IP Core Parameters
Parameter Value Description
Speed 10G, 1G/10G, 10M/100M/1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G Select the desired speed. By default, 10G is selected.
Datapath options TX only, RX only, TX & RX Select the MAC variation to instantiate.
  • TX only—instantiates MAC TX.
  • RX only—instantiates MAC RX.
  • TX & RX—instantiates both MAC TX and RX.
Enable ECC on memory blocks On, Off Turn on this option to enable error detection and correction on memory blocks. This option is available to designs that target Stratix® 10, Stratix® V, Arria® V GZ, Arria® 10, and Cyclone® 10 GX devices only.

When the IP core is generated with both the Enable time stamping and Enable ECC on memory blocks options enabled, all the memory blocks in the IP core are ECC protected except for the memory block related to the IEEE 1588v2 feature.

Enable preamble pass-through mode On, Off

Turn on this option to enable preamble pass-through mode. You must also set the tx_preamble_control, rx_preamble_control, and rx_custom_preamble_forward registers to 1. When enabled, the IP core allows custom preamble in data frames on the transmit and receive datapaths.

This option is available only for 10G.

Enable priority-based flow control (PFC) On, Off

Turn on this option to enable PFC. You must also set the tx_pfc_priority_enable[n]bit to 1 and specify the number of priority queues in the Number of PFC queues field.

This option is available only for 10G.

Number of PFC queues 2—8 Specify the number of PFC queues. This option is only enabled if you turn Enable priority-based flow control (PFC).
Enable unidirectional feature On, Off Turn on this option to enable unidirectional feature as specified in the IEEE802.3 specification (Clause 66). This feature is only supported in 10G, 1G/10G, and 1G/2.5G/10G speed mode.
Enable 10GBASE-R register mode On, Off

Turn on this option to enable 10GBASE-R register mode on the TX and RX datapaths to further reduce the round-trip latency between the MAC and the native PHY. In this mode, the MAC datapaths must run at 322.265625 MHz.

This option is available only for 10G TX & RX variation. It is not available with the following features:

  • preamble passthrough,
  • priority-based flow control,
  • unidirectional,
  • timestamping, and
  • 64-bit compatibility options on XGMII and Avalon® streaming interface.
Enable supplementary address On, Off Turn on this option to enable supplementary addresses. You must also set the EN_SUPP0/1/2/3 bits in the rx_frame_control register to 1.
Enable statistics collection On, Off Turn on this option to collect statistics on the TX and RX datapaths.
Statistics counters Memory-based, Register-based Specify the implementation of the statistics counters. When you turn on Statistics collection, the default implementation of the counters is Memory-based.
  • Memory-based—selecting this option frees up logic elements. The MAC IP core does not clear memory-based counters after they are read.
  • Register-based—selecting this option frees up the memory. The MAC IP core clears register-based statistic counters after the counters are read.

Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-to-back undersized frames. On the TX datapath, you can enable padding to avoid this situation. Undersized frames are frames with less than 64 bytes.

TX and RX datapath Reset/Default to Enable On, Off Turn off this option to disable TX and RX datapath during startup or CSR reset.
Note: This option is only available from Quartus® Prime Pro Edition version 18.0 onwards.
Enable time stamping On, Off Turn on this option to enable time stamping on the TX and RX datapaths. This option is not available in 1G/2.5G/10G ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G/5G/10G (USXGMII) ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
Enable PTP one-step clock support On, Off Turn on this option to enable 1-step time stamping. This option is enabled only when you turn on time stamping. This option is not available in 1G/2.5G/10G ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G/5G/10G (USXGMII) ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
Enable asymmetry support On, Off Turn on this option to enable asymmetry support on TX datapath. This option is enabled only when you turn on time stamping and PTP one-step clock support. This option is not available in 1G/2.5G/10G ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G/5G/10G (USXGMII) ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
Enable peer-to-peer On, Off Turn on this option to enable peer-to-peer support on TX datapath. This option is enabled only when you turn on time stamping and PTP one-step clock support. This option is not available in 1G/2.5G/10G ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/ 2.5G/5G/10G (USXGMII) ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
Note: This option is only available from Quartus® Prime Pro Edition version 17.0 onwards.
Timestamp fingerprint width 1–32 Specify the width of the timestamp fingerprint in bits on the TX path. The default value is 4 bits. This option is not available in 1G/2.5G/10G ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G/5G/10G (USXGMII) ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
Time of Day Format Enable 96b Time of Day Format only, Enable 64b Time of Day Format only, Enable both 96b and 64b Time of Day Format

Specify the time of day format. This option is not available in 1G/2.5G/10G ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G/5G/10G (USXGMII) ( Arria® 10 and Cyclone® 10 GX devices only), 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.

Use legacy Ethernet 10G MAC XGMII Interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the XGMII. This option is not available in 1G/2.5G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
Use legacy Ethernet 10G MAC Avalon® memory-mapped interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® memory-mapped interface. This option is not available in 1G/2.5G and 10M/100M/1G/2.5G configurations.
Use legacy Ethernet 10G MAC Avalon® streaming interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming interface. This option is not available in 1G/2.5G and 10M/100M/1G/2.5G configurations.
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