Stratix® 10 Embedded Memory User Guide

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ID 683423
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Embedded Memory Overview 2. Stratix® 10 Embedded Memory Architecture and Features 3. Stratix® 10 Embedded Memory Design Considerations 4. Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
1. Stratix® 10 Embedded Memory Overview x
1.1. Stratix® 10 Embedded Memory Features
2. Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Stratix® 10 Supported Embedded Memory IPs 2.11. Stratix® 10 Embedded Memory Clocking Modes 2.12. Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.8. True Dual Port Dual Clock Emulator x
2.8.1. Reducing the DCFIFO Depth
2.11. Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design 3.9. Resource and Timing Optimization Feature in MLAB Blocks 3.10. Consider the Memory Depth Setting 3.11. Consider Registering the Memory Output
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs 4.2. eSRAM Intel® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. FIFO2 Intel® FPGA IP 4.5. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® FPGA IP x
4.2.1. Release Information for eSRAM Intel® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® FPGA IP Parameters 4.2.4. eSRAM Intel® FPGA IP Interface Signals 4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 Intel® FPGA IP x
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 Intel® FPGA IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 Intel® FPGA IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 Intel® FPGA IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines
4.5. Shift Register (RAM-based) Intel® FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Intel Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide

7. Document Revision History for the Stratix® 10 Embedded Memory User Guide

Document Version Quartus® Prime Version Changes
2024.03.29 23.2 Changed DISABLE_EMBEDDED_TIMING_CONSTRAINT to DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT for lpm_hint parameter in the FIFO Parameter Settings.
2023.12.21 23.2
  • Updated the description for the Using the FIFO parameter editor method in Table Configuration Methods for clarity.
  • Added a new topic: Reducing the DCFIFO Depth.
2023.10.19 23.2 Updated Coherent Read Memory topic to replace the mention of "Wide simple dual-port" with "Simple dual-port with more than 20-bit wide data".
2023.06.26 23.2
  • Updated Table: FIFO2 Intel® FPGA IP Current Release Information.
  • Added Consider Registering the Memory Output topic.
2022.09.26 22.3
  • Added Resource and Timing Optimization Feature in MLAB Blocks topic.
  • Added Consider the Memory Depth Setting topic.
  • Updated the description for Same-Port Read-During-Write Mode and Mixed-Port Read-During-Write Mode.
2022.04.25 21.4 Updated the description for True Dual Port Dual Clock Emulator topic.
2022.01.12 21.4 Added a note for operation modes support in Stratix® 10 Embedded Memory Features topic.
2021.10.01 20.3
  • Updated "X" Propagation Support in Simulation.
  • Updated Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO.
2021.09.20 20.3
  • Updated the following topics:
    • Read/Write Clock
    • Input/Output Clock
  • Updated the description for Dual clock: use separate ‘input’ and ‘output’ clocks in Tables: RAM: 1-PORT Intel® FPGA IP Parameter Settings and RAM: 2-PORT Intel® FPGA IP Parameter Settings.
  • Updated the description in Reset Scheme for clarity.
2021.06.11 20.3
2021.03.29 20.3
  • Updated the data bits written in Table: Byte Enable Controls in ×40 Data Width (M20K).
  • Updated the Stratix® 10 Embedded Memory IP References to include information about inferring memory functions from HDL code.
  • Updated the following tables:
    • Mixed Port Read-During-Write Output Behaviors
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
    • RAM: 4-PORT Intel® FPGA IP Parameter Settings
    • ROM: 1-PORT Intel® FPGA IP Parameter Settings
    • ROM: 2-PORT Intel® FPGA IP Parameter Settings
    • eSRAM Intel® FPGA IP Parameter Editor: General Tab
    • FIFO Intel® FPGA IP Parameter Settings
2020.12.14 20.3
  • Added eSRAM Intel® FPGA IP information in Table: Stratix® 10 Memory IPs.
  • Updated the description in the Gray-Code Counter Transfer at the Clock Domain Crossing topic of the FIFO Intel® FPGA IP section.
2020.11.23 20.3 Updated Table: Shift Register (RAM-based) Intel® FPGA IP Parameter Settings to include information about Create a synchronous clear port.
2020.11.13 20.3 Updated the footnotes for aclr (synchronize with read clock) mode in Table: Asynchronous Clear in DCFIFO.
2020.10.12 20.3
  • Added the "X" Propagation Support in Simulation topic to describe about input signals supporting "X" value in simulation.
  • Added the Avoid Changing Clock Signals and Other Memory Signals Simultaneously topic to the Stratix® 10 Embedded Memory Design Considerations section.
  • Added the Shift Register (RAM-based) Intel FPGA IP section.
  • Removed the Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. parameter from the following tables:
    • Mixed Port Read-During-Write Output Behaviors
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
  • Updated the following parameter settings tab names in Table: RAM: 2-PORT Intel® FPGA IP Parameters Description:
    • Output 1 to Mixed Port Read-During-Write
    • Output 2 to Same Port Read-During-Write
  • Updated Tables: RAM: 1-PORT Intel® FPGA IP Parameters Description and RAM: 2-PORT Intel® FPGA IP Parameters Description to remove support for Use Stratix M512 emulation logic cell style for the LCs memory block type.
  • Updated the MLAB values for What is the width of a byte for byte enables? in Table: RAM: 1-PORT Intel® FPGA IP Parameters Description.
  • Updated Table: eSRAM Intel® FPGA IP Parameter Editor: General Tab to update the description for Enable Low Power Mode.
2020.08.03 20.1
  • Updated Table: Embedded Memory Capacity and Distribution in Stratix® 10 Devices to add resource counts for device GX 1660, GX 2110, GX 10M, TX 850, DX 1100, DX 2100, and DX2800.
  • Added a new topic to the Stratix® 10 Embedded Memory Design Considerations section—Including the Reset Release Intel® FPGA IP in Your Design.
  • Updated the True Dual Port Dual Clock Emulator section.
  • Updated Figure: Mixed-Port Read-During-Write: New_a_old_b Mode.
  • Updated the On Chip Memory RAM and ROM Intel® FPGA IPs section.
  • Updated the descriptions for the following parameters in Table: RAM: 1-PORT Intel® FPGA IP Parameters:
    • Create an ‘aclr’ asynchronous clear for the registered ports
    • Create an ‘sclr’ synchronous clear for the registered ports
  • Updated the description for clock0 in Table: Interface Signals of the Stratix® 10 RAM and ROM Intel® FPGA IP Cores.
2019.11.19 19.1
  • Updated Table: Mixed Port Read-During-Write Output Behaviors:
    • Updated the Output Data when Read-During-Write value of the constrained_dont_care and dont_care parameters from "New data" to "Don't care".
    • Added a footnote to state that the output data is "don't care" because the IP does not guarantee metastability for the output data when read-during-write.
  • Updated the FIFO Intel® FPGA IP section.
2019.10.17 19.1
  • Added new Topic—Avoid Providing Non-Deterministic Input.
  • Added a note to the RAM and ROM Interface Signals topic.
  • Updated the description for refclk signal in Table: eSRAM Intel® FPGA IP Input and Output Signals.
  • Updated Table: Stratix® 10 Memory IP Cores.
  • Updated Table: RAM: 2-PORT Intel® FPGA IP Parameter Settings:
    • Updated the legal values and description for What clocking method would you like to use?.
    • Updated the description for Enable Error Correction Check (ECC).
  • Updated Table: Parameters for altera_syncram.
2019.08.15 19.1
  • Updated the legal values and description for the What should the ‘q’ output be when reading from a memory location being written to? parameter in Table: RAM: 1-PORT Intel® FPGA IP Parameters Description.
  • Updated the description for the Get x’s for write masked bytes instead of old data when byte enable is used parameter in Table: RAM: 1-PORT Intel® FPGA IP Parameters Description.
2019.04.01 19.1
  • Updated the Byte Enable in Stratix® 10 Embedded Memory Blocks topic.
  • Updated Table: Byte Enable Controls in ×40 Data Width (M20K).
  • Updated the Customize Read-During-Write Behavior topic.
  • Updated the description for M20K blocks in the Memory Blocks Error Correction Code Support topic.
  • Updated Table: RAM: 2-PORT Intel® FPGA IP Parameter Settings to add notes to the Use clock enable for output registers (Clock Enables) and q_a port (Sclr Options) options.
  • Updated Table: RAM: 1-PORT Intel® FPGA IP Parameters Settings:
    • Added notes to the Use clock enable for output registers (Clock Enables) and q_a port (Sclr Options) options.
    • Updated the legal values and description for the Set the maximum block depth to parameter.
  • Updated Table: RAM: 2-PORT Intel® FPGA IP Parameters Settings to update the legal values for the Set the maximum block depth to parameter.
  • Updated Table: RAM: 4-PORT Intel® FPGA IP Parameters Settings to update the legal values for the Set the maximum block depth to parameter.
  • Made editorial and typographical updates throughout the document.
2018.12.24 18.1
  • Added a FIFO and FIFO2 Simulation Design Example section.
  • Updated the note in the True Dual Ports Dual Clock Emulator topic.
  • Added a note to Consider the Memory Block Selection topic.
  • Updated the Changing Parameter Settings Manually topic.
  • Made minor topic restructuring to the Intel Stratix 10 Embedded Memory Architecture and Features and the On Chip Memory RAM and ROM Intel FPGA IP Cores sections.
2018.10.24 18.1
  • Added a new topic: Initial Value of Read and Write Address Registers.
  • Updated True Dual Ports Dual Clock Emulator topic:
    • Updated the description for this topic.
    • Updated Table: Differences between Intel Arria 10 TDP Dual Clock Mode and Intel Stratix 10 Emulated TDP Dual Clock Mode to correct the device support for sclr.
    • Updated the following figures:
      • Output Condition of Port A
      • Output Condition of Port B
      • Read-During-Write Condition of Port A
      • Read-During-Write Condition of Port B
  • Renamed topic title Hardware Behavior to Consider the Concurrent Read Behavior.
  • Updated the following tables:
    • Intel Stratix 10 Embedded Memory Features
    • Embedded Memory Capacity and Distribution in Intel Stratix 10 Devices
    • RAM: 2-PORT Intel FPGA IP Parameter Settings
    • RAM: 4-PORT Intel FPGA IP Parameter Settings
    • ROM: 1-PORT Intel FPGA IP Parameter Settings
    • ROM: 2-PORT Intel FPGA IP Parameter Settings
    • Interface Signals of the Intel Stratix 10 RAM and ROM Intel FPGA IP Cores
  • Made minor editorial updates throughout the document.
Document Version Quartus® Prime Version Changes
2018.05.07 18.0
  • Updated the following IP cores as per Intel rebranding:
    • "RAM: 1-PORT" IP core to "RAM: 1-PORT Intel FPGA IP"
    • "RAM: 2-PORT" IP core to "RAM: 2-PORT Intel FPGA IP"
    • "RAM: 4-PORT" IP core to "RAM: 4-PORT Intel FPGA IP"
    • "ROM: 1-PORT" IP core to "ROM: 1-PORT Intel FPGA IP"
    • "ROM: 2-PORT" IP core to "ROM: 2-PORT Intel FPGA IP"
    • "Intel Stratix 10 Native eSRAM" IP core to "eSRAM Intel FPGA IP"
    • "FIFO" IP core to "FIFO Intel FPGA IP"
    • "FIFO2" IP core to "FIFO2 Intel FPGA IP"
  • Added new topics:
    • ECC Read-During-Write Behavior
    • Forwarding Logic
  • Updated Table: Intel Stratix 10 Embedded Memory Features:
    • Added Force-to-Zero support information
    • Removed packed mode feature.
  • Updated Table: Embedded Memory Capacity and Distribution in Intel Stratix 10 Devices to remove redundant table content on Intel Stratix 10 MX1650 and MX2100.
  • Updated the Memory Blocks Error Correction Code Support topic:
    • Updated the description for the ECC feature.
    • Updated the ECC status flag signals for eSRAM blocks
  • Updated the ECC Parity Flip topic to correct the parity bit sequence for double-adjacent-error correction.
  • Updated the Error Correction Code Truth Table topic:
    • Updated Figure: ECC Block Diagram for M20K Memory.
    • Update Table: ECC Status Flags Truth Table for eSRAM.
  • Updated the Force-to-Zero topic.
  • Updated the Coherent Read Memory topic:
    • Renamed topic title from Coherent Read to Coherent Read Memory.
    • Added new Figures: Coherent Read with Unregistered Output and Coherent Read with Registered Output.
    • Removed Figures: 1-level Pipelining Waveform and 2-level Pipelining Waveform.
  • Updated Table: Memory Blocks Clocking Modes Supported for Each Memory Mode to add a footnote for the read/write clock mode mode of true-dual-port mode.
  • Updated the Mixed-Width Port Configurations:
    • Added Table: Supported Mixed-width Ratios for Stratix® 10.
  • Removed Topic: Mixed-Width Ratio Configurations.
  • Updated the True Dual Ports Dual Clock Emulator topic:
    • Updated topic description to include information on valid signal.
    • Added new Figures:
      • Output Condition of Port A
      • Output Condition of Port B
      • RDW Condition of Port A
      • RDW Condition of Port B
  • Updated the Intel Stratix 10 Embedded Memory Configurations topic:
    • Updated Table: Supported Embedded Memory Block Configurations to correct the depth and programmable width for eSRAM.
    • Removed the note about Intel Stratix 10 devices do not natively support 1/32, 1/16, and 1/8 mixed-width port ratios.
  • Updated the Consider Power-Up State and Memory Initialization topic.
  • Updated Table: Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode to add a note include a note for Don't Care mode.
  • Added a Table: Mixed Port Read-During-Write Output Behaviors.
  • Updated the RAM and ROM Intel FPGA IP Core chapter:
    • Added Changing Parameter Settings Manually and RAM and ROM Parameters subtopics.
    • Updated Tables:
      • RAM: 1-PORT Intel FPGA IP Core Parameter Settings
      • RAM: 2-PORT Intel FPGA IP Core Parameter Settings
      • RAM: 4-PORT Intel FPGA IP Core Parameter Settings
      • ROM: 2-PORT Intel FPGA IP Core Parameter Settings
      • ROM: 2-PORT Intel FPGA IP Core Parameter Settings
      • Interface Signals of the RAM and ROM Intel FPGA IP Cores
  • Updated the eSRAM Intel FPGA IP
    • Updated Table: eSRAM Specifications:
      • Added a footnote to the clock frequency feature.
      • Corrected the clock frequency value of -2 speed grade from 200 MHz - 650 MHz to 200 MHz - 640 MHz.
      • Updated the write latency value from 0 to 0 + 1.
      • Added a footnote to the write latency feature.
    • Updated Table: eSRAM Intel FPGA IP Core Parameter Editor: Channel Tab.
    • Updated Table: eSRAM Intel FPGA IP Core Input and Output Signals:
      • Added a new interface signal—iopll_lock2core.
      • Updated the width of the esram2f_clk signal from 2 to 1.
      • Updated the description of the esram2f_clk signal.
      • Updated the width of c<channel_number>_data_0 signal from '72 or 64' to '1-72'.
    • Updated the eSRAM Intel FPGA IP Simulation Walkthrough topic.
  • Updated FIFO Intel FPGA IP chapter:
    • Added Reset Scheme subtopic.
  • Updated the FIFO2 Intel FPGA IP chapter:
    • Updated Table: Differences between FIFO and FIFO2 Intel FPGA IP Cores to remove the reset scheme feature.
    • Updated Table: FIFO2 Specifications:
      • Added a footnote for M20K of the Error Checking and Correcting (ECC) feature.
      • Updated the description for MLAB of the Targeted Performance feature.
    • Renamed topic title FIFO2 User-Configurable Parameters to FIFO2 Parameter Settings.
    • Updated Figure: FIFO2 IP Core Input and Output Signals.
    • Updated Tables: SCFIFO Input and Output Ports Description and DCFIFO Input and Output Ports Description to include descriptions for w_ready signal.
  • Updated for latest Intel branding standards.
  • Made editorial updates throughout the document.
Date Version Changes
December 2017 2017.12.04 Updated the "Embedded Memory Capacity and Distribution in Intel Stratix 10 Devices" table: Corrected the total RAM Bit (Mbits) for Intel Stratix 10 GX, Intel Stratix 10 MX, and Intel Stratix 10 SX variants.
November 2017 2017.11.06
  • Added a new feature—True Dual Ports Dual Clock Emulator.
  • Updated the Intel Stratix 10 Embedded Memory Features topic: Updated the number of banks for each channel in the eSRAM blocks from 40 banks to 42 banks.
  • Updated the "Intel Stratix 10 Embedded Memory Features" table:
    • Updated the description for eSRAM for the Mixed-port read-during-write and coherent read features.
    • Added freeze logic, hardware behavior, and TDP dual clock emulator features.
  • Updated the "Embedded Memory Capacity and Distribution in Intel Stratix 10 Devices" table:
    • Updated eSRAM block and RAM (Bit) values for Intel Stratix 10 GX and Intel Stratix 10 SX variants.
    • Added embedded memory capacity information for Intel Stratix 10 MX variant.
    • Updated the values of M20K and MLAB RAM Bits, and total RAM bits for TX1650 and TX2100 product lines for Intel Stratix 10 TX variant.
  • Updated the Byte Enable in Intel Stratix 10 Embedded Memory Blocks topic.
  • Updated the Data Byte Output subtopic.
  • Updated the Asynchronous Clear and Synchronous Clear topic:
    • Updated the topic description.
    • Updated Figures: "Behavior of Asynchronous Clear and Synchronous Clear In Registered Mode" and "Behavior for Asynchronous Clear and Synchronous Clear In Unregistered Mode".
  • Updated the Memory Blocks Error Correction Code Support topic:
    • Added a feature for memory blocks error correction code support—ECC Parity Flip.
    • Updated the description of the eSRAM Blocks.
  • Added "ECC Status Flags Truth Table for eSRAM" table in the Error Correction Code Truth Table subtopic.
  • Updated the Embedded Memory Operating Modes topic;
    • Renamed topic as Intel Stratix 10 Embedded Memory Supported IP Cores.
    • Updated "Intel Stratix 10 Memory IP Cores" table: Added IP Core column and information for ROM: 2 PORT.
  • Updated the "Memory Blocks Clocking Modes Supported for Each Memory Mode" table:
    • Added Dual-Port ROM memory mode.
    • Added input/output clock mode support for True Dual-Port.
    • Removed FIFO memory mode.
  • Updated the note for the simple dual-port mode in the Mixed-Width Ratio Configuration topic.
  • Updated the "RAM in Mixed-Port Read-During-Write Mode" table:
    • Added a note to the Don't Care description for the Don't Care mode.
    • Added New_a_old_b mode to the table.
    • Added new Figure—Mixed-Port Read-During-Write: New_a_old_b Mode.
  • Updated the RAM: 1-PORT and RAM: 2-PORT IP cores topics in the On-Chip Memory RAM and ROM IP Cores section.
  • Updated the "RAM: 2-Port Parameter Setting" table: Added the Emulate TDP dual clock mode option.
  • Updated the "Interface Signals of the Intel Stratix 10 On-Chip Memory RAM and ROM IP Cores" table:
    • Updated the direction values for eccencbypass and eccencparity signals.
    • Added three signals—address2_a, address2_b, and sclr.
    • Removed four signals: clocken2, clocken3, aclr0, and aclr1.
    • Updated the description for aclr signal.
  • Renamed the topic Intel Stratix 10 eSRAM IP Core to Intel Stratix 10 Native eSRAM IP Core to align with Intel Quartus Prime naming.
  • Added eSRAM IP core references to the Intel Stratix 10 Native eSRAM IP Core topic.
  • Added FIFO IP core references to the FIFO IP Core topic.
  • Added FIFO2 IP core references to the FIFO2 IP Core topic.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
May 2017 2017.05.08
  • Removed parity bit support for MLAB blocks under the Error Correction Code (ECC) support feature in the Stratix® 10 Embedded Memory Features table.
  • Updated the descriptions for M20K and MLAB blocks under Error Correction code (ECC) support feature in the Stratix® 10 Embedded Memory Features table.
  • Updated the Embedded Memory Capacity and Distribution in Stratix® 10 Devices table to remove TX4500 and TX5500, which are no longer part of Stratix® 10 TX variant.
  • Updated the Byte Enable Controls in ×10 Data Width (MLAB) table.
  • Removed parity bit support for MLAB blocks in the Parity Bit topic.
  • Added notes to the Supported Embedded Memory Block Configurations table in the Stratix® 10 Embedded Memory Configurations topic.
  • Added Mixed-Width Ratio Configurations topic.
  • Added Freeze Logic topic.
  • Added the Implement clock-enable circuitry for use in a partial reconfiguration region option for the RAM: 1-PORT, RAM: 2-PORT, and RAM: 4-PORT IP cores.
  • Removed the Use different data widths on different ports option from RAM: 4-Port Parameter Settings table because this option is not available in RAM: 4-Port.
  • Added Hardware Behavior topic.
  • Added figures for the Coherent Read topic.
  • Updated the feature description for ROM: 1-PORT and ROM: 2-PORT in the table of the On-Chip Memory RAM and ROM IP Cores topic.
  • Added ecc_enc_bypass and ecc_enc_parity signals in the Interface Signals of the Stratix® 10 On-Chip Memory RAM and ROM IP Cores table.
  • Added Stratix® 10 eSRAM IP core topic.
  • Minor typographical corrections.
October 2016 2016.10.31 Initial release
Level Two Title