Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 9/26/2022
Public

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4.4.2. Configuration Methods

Table 57.  Configuration MethodsYou can configure and build the FIFO2 Intel® FPGA IP cores with methods shown in the following table.
Method Description
Using the FIFO2 parameter editor. Intel® recommends using this method to build your FIFO2 Intel® FPGA IP cores. It is an efficient way to configure and build the FIFO2 Intel® FPGA IP cores. The FIFO2 parameter editor provides options that you can easily use to configure the FIFO2 Intel® FPGA IP core.

You can access the FIFO2 Intel® FPGA IP core parameter editor in Basic Functions > On Chip Memory > FIFO2 of the IP catalog.45

Manually instantiating the FIFO2 Intel® FPGA IP cores. Use this method only if you are an expert user. This method requires that you know the detailed specifications of the IP cores. You must ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO2 Intel® FPGA IP cores you instantiate for your target device.
45 Do not use dcfifo or scfifo as the entity name for your FIFO2 Platform Designer system.