Visible to Intel only — GUID: bhc1411020033535
Ixiasoft
Visible to Intel only — GUID: bhc1411020033535
Ixiasoft
7.7. Underflow and Overflow
Underflow
The FIFO buffer can accommodate any bursts if the output rate of the downstream Avalon streaming video components is equal to or higher than that of the outgoing clocked video. If not , the FIFO underflows. If underflow occurs, the CVO IP continues to produce video and resynchronizing the startofpacket for the next image packet, from the Avalon streaming video interface with the start of the next frame. You can detect the underflow by looking at bit 2 of the Status register. This bit is sticky and if an underflow occurs, it stays at 1 until the bit is cleared by writing a 1 to it.
Overflow
The FIFO buffer can accommodate any bursts if the input rate of the upstream Avalon streaming video components is equal to or higher than that of the incoming clocked video. If not, the FIFO overflows. If overflow occurs, the IP produces an early endofpacket signal to complete the current frame. It then waits for the next start of frame (or field) before resynchronizing to the incoming clocked video and beginning to produce data again. The overflow is recorded in bit [9] of the Status register. This bit is sticky, and if an overflow occurs, it stays at 1 until the bit is cleared by writing a 0 to it. In addition to the overflow bit, you can read the current level of the FIFO buffer from the Used Words register.
The IP uses the height and width parameters at the point the frame was completed early in the control packet of the subsequent frame. If you are reading back the detected resolution, these unusual resolution values can make the IP seem to be operating incorrectly. When actually, the downstream system is failing to service the CVI IP at the necessary rate.