Video and Image Processing Suite User Guide

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ID 683416
Date 4/04/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Image Processing Suite 2. Avalon Streaming Video 3. Clocked Video 4. VIP Run-Time Control 5. Getting Started 6. VIP Connectivity Interfacing 7. Clocked Video Interface IPs 8. 2D FIR II IP Core 9. Mixer II IP Core 10. Clipper II IP Core 11. Color Plane Sequencer II IP Core 12. Color Space Converter II IP Core 13. Chroma Resampler II IP Core 14. Control Synchronizer IP Core 15. Deinterlacer II IP Core 16. Frame Buffer II IP Core 17. Gamma Corrector II IP Core 18. Configurable Guard Bands IP Core 19. Interlacer II IP Core 20. Scaler II IP Core 21. Switch II IP Core 22. Test Pattern Generator II IP Core 23. Trace System IP Core 24. Warp Lite Intel FPGA IP 25. Avalon-ST Video Stream Cleaner IP Core 26. Avalon-ST Video Monitor IP Core 27. VIP IP Core Software Control 28. Security Considerations 29. Video and Image Processing Suite User Guide Archives 30. Document Revision History for the Video and Image Processing Suite User Guide A. Avalon-ST Video Verification IP Suite
1. About the Video and Image Processing Suite x
1.1. Release Information 1.2. Device Family Support 1.3. Latency 1.4. In-System Performance and Resource Guidance 1.5. Stall Behavior and Error Recovery
2. Avalon Streaming Video x
2.1. Avalon-ST Video Configuration Types 2.2. Avalon-ST Video Packet Types 2.3. Avalon-ST Video Operation 2.4. Avalon-ST Video Error Cases
2.2. Avalon-ST Video Packet Types x
2.2.1. Avalon-ST Video Control Packets 2.2.2. Avalon-ST Video Video Packets 2.2.3. Avalon-ST Video User Packets
3. Clocked Video x
3.1. Video Formats
3.1. Video Formats x
3.1.1. Embedded Synchronization Format: Clocked Video Output 3.1.2. Embedded Synchronization Format: Clocked Video Input 3.1.3. Separate Synchronization Format 3.1.4. Video Locked Signal 3.1.5. Clocked Video and 4:2:0 Chroma Subsampling
3.1.1. Embedded Synchronization Format: Clocked Video Output x
3.1.1.1. Clocked Video Output and SDI II TX Interface
3.1.5. Clocked Video and 4:2:0 Chroma Subsampling x
3.1.5.1. Avalon-ST Video Control Packets for 4:2:0 Video 3.1.5.2. 4:2:0 Clocked Video 3.1.5.3. Resampling 4:2:0
5. Getting Started x
5.1. IP Catalog and VIP Parameter Editor 5.2. Installing and Licensing IP Cores
5.1. IP Catalog and VIP Parameter Editor x
5.1.1. Specifying IP Core Parameters and Options
5.2. Installing and Licensing IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
6. VIP Connectivity Interfacing x
6.1. Avalon-ST Color Space Mappings
6.1. Avalon-ST Color Space Mappings x
6.1.1. Interfacing with High-Definition Multimedia Interface (HDMI) 6.1.2. Interfacing with DisplayPort 6.1.3. Interfacing with Serial Digital Interface (SDI) 6.1.4. Unsupported SDI Mappings 6.1.5. 12G-SDI
6.1.5. 12G-SDI x
6.1.5.1. 12G-SDI with Clocked Video Input II 6.1.5.2. 12G-SDI with Clocked Video Output II
7. Clocked Video Interface IPs x
7.1. Supported Features for Clocked Video Output II IP 7.2. Control Port 7.3. Clocked Video Input IP Format Detection 7.4. Clocked Video Output IP Video Modes 7.5. Clocked Video Output II Latency Mode 7.6. Generator Lock 7.7. Underflow and Overflow 7.8. Timing Constraints 7.9. Handling Ancillary Packets 7.10. Modules for Clocked Video Input II IP Core 7.11. Clocked Video Input II Signals, Parameters, and Registers 7.12. Clocked Video Output II Signals, Parameters, and Registers
7.3. Clocked Video Input IP Format Detection x
7.3.1. Format Detection in Clocked Video Input II 7.3.2. Interrupts
7.4. Clocked Video Output IP Video Modes x
7.4.1. Interrupts
7.11. Clocked Video Input II Signals, Parameters, and Registers x
7.11.1. Clocked Video Input II Interface Signals 7.11.2. Clocked Video Input II Parameter Settings 7.11.3. Clocked Video Input II Control Registers
7.12. Clocked Video Output II Signals, Parameters, and Registers x
7.12.1. Clocked Video Output II Interface Signals 7.12.2. Clocked Video Output II Parameter Settings 7.12.3. Clocked Video Output II Control Registers
8. 2D FIR II IP Core x
8.1. 2D FIR Filter Processing 8.2. 2D FIR Filter Precision 8.3. 2D FIR Coefficient Specification 8.4. 2D FIR Filter Symmetry 8.5. Result to Output Data Type Conversion 8.6. Edge-Adaptive Sharpen Mode 8.7. 2D FIR Filter Parameter Settings 8.8. 2D FIR Filter Control Registers
8.4. 2D FIR Filter Symmetry x
8.4.1. No Symmetry 8.4.2. Horizontal Symmetry 8.4.3. Vertical Symmetry 8.4.4. Horizontal and Vertical Symmetry 8.4.5. Diagonal Symmetry
8.6. Edge-Adaptive Sharpen Mode x
8.6.1. Edge Detection 8.6.2. Filtering 8.6.3. Precision
9. Mixer II IP Core x
9.1. Alpha Blending 9.2. Mixer II Parameter Settings 9.3. Mixer II Control Registers 9.4. Layer Mapping 9.5. Low-Latency Mode
10. Clipper II IP Core x
10.1. Clipper II Parameter Settings 10.2. Clipper II Control Registers
11. Color Plane Sequencer II IP Core x
11.1. Combining Color Patterns 11.2. Rearranging Color Patterns 11.3. Splitting and Duplicating 11.4. Handling of Subsampled Data 11.5. Handling of Non-Image Avalon-ST Packets 11.6. Color Plane Sequencer Parameter Settings
12. Color Space Converter II IP Core x
12.1. Input and Output Data Types 12.2. Color Space Conversion 12.3. Result of Output Data Type Conversion 12.4. Color Space Converter Parameter Settings 12.5. Color Space Conversion Control Registers
12.2. Color Space Conversion x
12.2.1. Predefined Conversions
13. Chroma Resampler II IP Core x
13.1. Chroma Resampler Algorithms 13.2. Chroma Resampler Parameter Settings 13.3. Chroma Resampler Control Registers
13.1. Chroma Resampler Algorithms x
13.1.1. Nearest Neighbor 13.1.2. Bilinear 13.1.3. Filtered
14. Control Synchronizer IP Core x
14.1. Using the Control Synchronizer IP Core 14.2. Control Synchronizer Parameter Settings 14.3. Control Synchronizer Control Registers
15. Deinterlacer II IP Core x
15.1. Deinterlacing Algorithm Options 15.2. Deinterlacing Algorithms 15.3. Run-time Control 15.4. Pass-Through Mode for Progressive Frames 15.5. Cadence Detection (Motion Adaptive Deinterlacing Only) 15.6. Avalon-MM Interface to Memory 15.7. Motion Adaptive Mode Bandwidth Requirements 15.8. Avalon-ST Video Support 15.9. 4K Video Passthrough Support 15.10. Behavior When Unexpected Fields are Received 15.11. Handling of Avalon-ST Video Control Packets 15.12. Deinterlacer II Parameter Settings 15.13. Deinterlacing Control Registers
15.2. Deinterlacing Algorithms x
15.2.1. Vertical Interpolation (Bob) 15.2.2. Field Weaving (Weave) 15.2.3. Motion Adaptive 15.2.4. Motion Adaptive High Quality (Sobel Edge Interpolation)
15.9. 4K Video Passthrough Support x
15.9.1. Approach A 15.9.2. Approach B
15.13. Deinterlacing Control Registers x
15.13.1. Scene Change Motion Multiplier Value 15.13.2. Tuning Motion Shift and Motion Scale Registers
16. Frame Buffer II IP Core x
16.1. Double Buffering 16.2. Triple Buffering 16.3. Locked Frame Rate Conversion 16.4. Handling of Avalon-ST Video Control Packets and User Packets 16.5. Frame Buffer Parameter Settings 16.6. Frame Buffer Application Examples 16.7. Frame Buffer Control Registers
16.3. Locked Frame Rate Conversion x
16.3.1. Converting Frame Rates
16.7. Frame Buffer Control Registers x
16.7.1. Frame Writer Only Mode 16.7.2. Frame Reader Only Mode 16.7.3. Memory Map for Frame Reader or Writer Configurations
17. Gamma Corrector II IP Core x
17.1. Gamma Corrector Parameter Settings 17.2. Gamma Corrector Control Registers
18. Configurable Guard Bands IP Core x
18.1. Guard Bands Parameter Settings 18.2. Configurable Guard Bands Control Registers
19. Interlacer II IP Core x
19.1. Interlacer Parameter Settings 19.2. Interlacer Control Registers
20. Scaler II IP Core x
20.1. Nearest Neighbor Algorithm 20.2. Bilinear Algorithm 20.3. Polyphase and Bicubic Algorithm 20.4. Edge-Adaptive Scaling Algorithm 20.5. Scaler II Parameter Settings 20.6. Scaler II Control Registers
20.2. Bilinear Algorithm x
20.2.1. Bilinear Algorithmic Description
20.3. Polyphase and Bicubic Algorithm x
20.3.1. Double-Buffering 20.3.2. Polyphase Algorithmic Description 20.3.3. Choosing and Loading Coefficients
21. Switch II IP Core x
21.1. Switch II Parameter Settings 21.2. Switch II Control Registers
22. Test Pattern Generator II IP Core x
22.1. Test Patterns 22.2. Output Subsampling and Color Space 22.3. Generation of Avalon-ST Video Control Packets and Run-Time Control 22.4. Test Pattern Generator II Parameter Settings 22.5. Test Pattern Generator II Control Registers
22.1. Test Patterns x
22.1.1. Color Bars 22.1.2. Grayscale Bars 22.1.3. Black and White Bars 22.1.4. SDI Pathological 22.1.5. Uniform Background
23. Trace System IP Core x
23.1. Trace System Parameter Settings 23.2. Trace System Signals 23.3. Operating the Trace System from System Console
23.3. Operating the Trace System from System Console x
23.3.1. Loading the Project and Connecting to the Hardware 23.3.2. Trace Within System Console 23.3.3. TCL Shell Commands
24. Warp Lite Intel FPGA IP x
24.1. Warp Lite IP Release Information 24.2. About Image Warping 24.3. About the Warp Lite Intel FPGA IP 24.4. Operating the Warp Lite IP 24.5. Warp Lite IP Parameters 24.6. Warp Lite IP Control Registers' Map 24.7. Warp Lite IP Line Store 24.8. Warp Lite IP API
24.3. About the Warp Lite Intel FPGA IP x
24.3.1. Warp Definition Equations 24.3.2. Resampling and Interpolation
24.3.1. Warp Definition Equations x
24.3.1.1. Transform Matrix and Keystone Region Corners 24.3.1.2. Horizontal Flip Equation
24.7. Warp Lite IP Line Store x
24.7.1. Line Store RAM Utilization 24.7.2. Buffer Ingress and Egress Overlap
25. Avalon-ST Video Stream Cleaner IP Core x
25.1. Avalon-ST Video Protocol 25.2. Repairing Non-Ideal and Error Cases 25.3. Avalon-ST Video Stream Cleaner Parameter Settings 25.4. Avalon-ST Video Stream Cleaner Control Registers
26. Avalon-ST Video Monitor IP Core x
26.1. Packet Visualization 26.2. Monitor Settings 26.3. Avalon-ST Video Monitor Parameter Settings 26.4. Avalon-ST Video Monitor Control Registers
27. VIP IP Core Software Control x
27.1. HAL Device Drivers for Nios II SBT
28. Security Considerations x
28.1. Using Avalon-ST Video Monitor Debug Tools 28.2. Configuring Memory Subsystems
A. Avalon-ST Video Verification IP Suite x
A.1. Avalon-ST Video Class Library A.2. Example Tests A.3. Complete Class Reference A.4. Data Format
A.2. Example Tests x
A.2.1. Generating the Testbench Netlist A.2.2. Running the Test in Intel® Quartus® Prime Standard Edition A.2.3. Running the Test in Intel® Quartus® Prime Pro Edition A.2.4. Viewing the Video File A.2.5. Verification Files A.2.6. Constrained Random Test
A.2.5. Verification Files x
A.2.5.1. bfm_drivers.sv A.2.5.2. nios_control_model.sv
A.3. Complete Class Reference x
A.3.1. c_av_st_video_control A.3.2. c_av_st_video_data A.3.3. c_av_st_video_file_io A.3.4. c_av_st_video_item A.3.5. c_av_st_video_source_sink_base A.3.6. c_av_st_video_sink_bfm_’SINK A.3.7. c_av_st_video_source_bfm_’SOURCE A.3.8. c_av_st_video_user_packet A.3.9. c_pixel A.3.10. av_mm_transaction A.3.11. av_mm_master_bfm_`MASTER_NAME A.3.12. av_mm_slave_bfm_`SLAVE_NAME A.3.13. av_mm_control_register A.3.14. av_mm_control_base
1. About the Video and Image Processing Suite
2. Avalon Streaming Video
3. Clocked Video
4. VIP Run-Time Control
5. Getting Started
6. VIP Connectivity Interfacing
7. Clocked Video Interface IPs
8. 2D FIR II IP Core
9. Mixer II IP Core
10. Clipper II IP Core
11. Color Plane Sequencer II IP Core
12. Color Space Converter II IP Core
13. Chroma Resampler II IP Core
14. Control Synchronizer IP Core
15. Deinterlacer II IP Core
16. Frame Buffer II IP Core
17. Gamma Corrector II IP Core
18. Configurable Guard Bands IP Core
19. Interlacer II IP Core
20. Scaler II IP Core
21. Switch II IP Core
22. Test Pattern Generator II IP Core
23. Trace System IP Core
24. Warp Lite Intel FPGA IP
25. Avalon-ST Video Stream Cleaner IP Core
26. Avalon-ST Video Monitor IP Core
27. VIP IP Core Software Control
28. Security Considerations
29. Video and Image Processing Suite User Guide Archives
30. Document Revision History for the Video and Image Processing Suite User Guide
A. Avalon-ST Video Verification IP Suite

30. Document Revision History for the Video and Image Processing Suite User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.04.04 22.1
  • Added support for Intel® Agilex™ devices.
  • Added Frame Buffer II to Minimum and Maximum Supported X and Y Resolutions table
2021.02.12 19.4 Removed Clocked Video Input IP and Clocked Video Output IP.
2020.12.12 19.4 Updated Clipper IP Parameters
2020.10.30 19.4
  • Enhanced H-sync and V-sync polarity description in Clocked Video Output II Registers table.
  • Added extra info to Locked Frame Rate Conversion.
2020.03.10 19.4 Corrected CVI to CVO in the sentence:
  • A CVO IP core can take in the locked PLL clock and the SOF signal.
2020.02.06 19.4 Extended the ready signal to high before cycle 0 on Avalon-ST Video Packet Transmission (Symbols in Parallel) figure.
2019.12.10 19.4 Added Warp Intel FPGA IP.
2019.07.10 19.1 Edited typo in lines 99 and 112 in testbench/bfm_drivers.sv. (step 1c) in the Running the Test in Intel® Quartus® Prime Pro Edition section.
2019.04.22 19.1
  • Added support for Intel® Stratix® 10 devices.
  • Added a new section about interfacing the clocked video output with the SDI II IP core. The Clocked Video and SDI II TX Interface section provides information about the behavior of the relevant signals and the supported cadence.
  • Updated the 12G-SDI section to include more information about the support for 6G-SDI and 12G-SDI and added specific sections for CVI II and CVO II IP cores that also include the SDI resampler information.
  • Added 12G-SDI in the list of supported features for CVO II IP core in the Supported Features for Clocked Video Output IP Cores section.
  • Added a note that for 3G, 6G, and 12G modes, the CVI II IP core only supports YCbCr input color format with either 8 or 10 bits for each component.in the Clocked Video Input Format Detection section.
  • Added information about SDC warning messages for CVI II and CVO II IP cores in the Timing Constraints section.
  • Added information about the Sdi_resampler module in the Modules for Clocked Video Input II Intel FPGA IP section.
  • Updated the Clocked Video Input II Parameter Settings section.
    • Added description for the Support 6G and 12G-SDI parameter. Turn on this parameter to enable 6G-SDI or 12G-SDI support.
    • Updated the description for the Width of vid_std_bus parameter to include information about embedded sync. The width of the vid_std bus must be 3 bits.
  • Updated the Clocked Video Output II Parameter Settings section.
    • Added description for the Support 6G and 12G-SDI parameter. Turn on this parameter to enable 6G-SDI or 12G-SDI support.
    • Added description for the Default SDI video standard parameter. This parameter allows you to set the default SDI standard. To use 6G-SDI or 12G-SDI standards, you must turn on Support 6G and 12G-SDI.
    • Updated the description for the Width of vid_std_bus parameter to include information about embedded sync. The width of the vid_std bus must be 3 bits.
  • Added description for the sdi_cvo_rden signal in the Clocked Video Output II Interface Signals section. This signal connects to the SDI II IP core's tx_dataout_valid output signal.
  • Updated the Behavior When Unexpected Fields are Received section in the Deinterlacer II IP Core chapter.
  • Added a new option (512) for the Avalon-MM master(s) local ports width parameter in the Deinterlacer II Parameter Settings section.
  • Removed outdated information and updated the description in the Deinterlacing Control Registers section.
  • Added a note that for security reasons, you should remove the Trace System components from designs going to production in the Trace System IP Core section. This IP core is meant only for Intel® Quartus® Prime Standard Edition environments.
  • Removed the information about avi2raw and raw2avi utilities from the Avalon-ST Video Verification IP Suite appendix section because this functionality is available in the open source FFmpeg tool (ffmpeg.org).
2018.09.24 18.1
  • Edited the Device Family Support section to clearly indicate that the VIP Suite IP cores support Arria® V GZ and Cyclone® IV E variants.
  • Added new features for the Deinterlacer II IP core:
    • New run-time control and status registers to improve deinterlacing quality for mid-range motion-adaptive configurations.
    • New run-time control registers to allow run-time switching between “bob”, ”weave” and “motion adaptive” modes.
  • Added Native 4K HDR/SDR Passthrough support information for the Deinterlacer II IP core in the Deinterlacing Algorithm Options section.
  • Updated the 4K Video Passthrough Support section to add information about determining best approaches for 4K passthrough for Deinterlacer II IP core configurations.
  • Edited the existing and added new registers for the Deinterlacer II IP core in the Deinterlacing Control Registers section.
  • Updated the description for the parameters for the Deinterlacer II IP core:
  • Updated the introduction description for the Test Pattern Generator II IP core. The IP core now offers five test pattern options and supports up to 8 pixels per cycle.
  • Added information about the five test patterns for the Test Pattern Generator II IP core: Color bars, Grayscale bars, Black and White bars, SDI Pathological, and Uniform Background
  • Added information about output subsampling and color space for the Test Pattern Generator II IP core.
  • Updated or added the following parameters for the Test Pattern Generator II IP core:
    • Output format
    • Default interlacing
    • Run-time control
    • Reduced control register readback
    • Pipeline dout ready
    • Enable border for bar patterns
    • Uniform
    • Number of test patterns
    • Subsampling & Colorspace
  • Updated the Test Pattern Generator II Control Register Map table with the latest addresses and registers.
  • Updated the Mixer II IP Core introduction section to add information about the new Synchronize background to layer 0 parameter.
  • Updated the Mixer II feature information to add that now the Mixer II IP core supports up to 20 inputs and up to 8 pixels in parallel..
  • Updated or added following parameters for the Mixer II IP core:
    • Number of inputs
    • Alpha Blending Enable
    • InputN alpha channel
    • Synchronize background to layer 0
    • Reduced control register readback
    • Add extra register stages to data pipeline
  • Updated the Alpha Blending Enable section for the Mixer II IP core to add information about the new InputN alpha channel parameter.
  • Updated the description for the Background Width and Background Height Mixer II registers to add that these registers are not available when the Synchronize background to layer 0 parameter is enabled.
  • Add a new section on Low-Latency Mode for the Mixer II IP core.
  • Updated the Switch II feature information to add that now the Switch II IP core supports up to 8 pixels in parallel and added a note that the function of the status bit for the Switch II IP core differs from the status bits of the other VIP IP cores.
2018.07.20 18.0 Corrected the error in the description for the Scaler II input and output frame widths and heights in the Scaler II parameter settings. The supported maximum widths and heights are 8,192.
2018.05.07 18.0
  • Added a table in the Video and Image Processing IP Cores introduction section to list the minimum and maximum input/output resolutions.
  • Edited the Progressive interlacing values in the Avalon-ST Video Control Packet Interlaced Nibble Decoding table.
  • Added a note in the Avalon-ST Operation section that some VIP IP cores require a control packet to initialize storage. To ensure correct operation across all VIP components, at least one control packet must be sent to an IP core prior to any video packets.
  • Added a caution note in the Avalon-ST Video Support section that some memory configurations for motion adaptive configurations of the Deinterlacer II (but not video over film configurations) can result in motion information being incorrectly overwritten by information from subsequent lines, resulting in a reduction in QOR manifesting in weave artifacts.
  • Added a note that the VIP IP cores support only ModelSim* simulation software in the Specifying IP Core Parameters and Options section.
  • Edited the register bits width for the Frame Buffer II IP core. The actual width is 32 bits.
  • Updated the maximum frame width and height from 4096 to 8192 for the following FPGA IP cores:
    • Avalon-ST Video Stream Cleaner
    • Clipper II
    • Clocked Video Input II
    • Deinterlacer II
    • Frame Buffer II
    • Mixer II
    • Scaler II
    • Test Pattern Generator II
  • Added a new option (8) for the Number of pixels in parallel parameter for the following IP cores:
    • 2D FIR Filter II
    • Avalon-ST Video Stream Cleaner
    • Chroma Resampler II
    • Clipper II
    • Clocked Video Input II
    • Clocked Video Output II
    • Color Space Converter II
    • Deinterlacer II
    • Frame Buffer II
    • Gamma Corrector II
    • Configurable Guard Bands
    • Interlacer II
    • Mixer II
    • Scaler II
    • Switch II
    • Test Pattern Generator II
  • Added information about the acknowledge bit for the Misc register in the Frame Buffer Control Registers section.
  • Removed note that stated the Clocked Video Output II IP core does not support Genlock. The Clocked Video Output II IP core now supports Genlock.
  • Added new parameters for Clocked Video Output II IP core:
    • Generate Synchronization outputs
    • Accept Synchronization inputs
    • Set vco_clk_divider increment to pixels in parallel
  • Added Genlock signals for Clocked Video Output II IP core:
    • vid_vcoclk_div
    • vid_sof
    • vid_sof_locked
    • sof
    • sof_locked
  • Added information that ModeN SOF Line is a 13-bit register and ModeN Vcoclk Divider is a 14-bit register in the Clocked Video Output II Registers table.
  • Edited the description for the sof_locked signal in the Clocked Video Output Signals table. This signal is an input signal.
Date Version Changes
November 2017 2017.11.06
  • Updated support for Intel® Cyclone® 10 LP and Intel® Cyclone® 10 GX devices as final.
  • Changed the term Qsys to Platform Designer.
  • Made extensive changes to the Avalon-ST Video Verification IP Suite section based on the changes in the Intel® Quartus® Prime software.
  • Changed the minimum width and height values to 32 in the Clipper II Parameter Settings section.
  • Added a note that if you have enabled run-time control, the Go bit gets deasserted by default for the following IP cores:
    • 2D FIR Filter II
    • Clipper II
    • Deinterlacer II
    • Scaler II
    • Frame Buffer II
    • Configurable Guard Bands
    • Interlacer II
    • Scaler II
    • Test Pattern Generator II
  • Added a note that the following IP cores require even frame widths when using 4:2:2 data; odd frames widths create unpredictable results or distorted images:
    • 2D FIR Filter II
    • Deinterlacer II
    • Scaler II
    • Configurable Guard Bands
    • Scaler II
    • Mixer II
    • Test Pattern Generator II
  • Added information that if new frame dimensions are set, the Frame Buffer II IP core requires a write to the Frame Start Address register for the new settings to take effect.
  • Added new parameters for Frame Buffer II IP core:
    • Delay length (frames)
    • Drop/repeat user packets
  • Edited the Reduced control register readback parameter information for the Gamma Corrector IP core that only values written to registers 5 and 6 in the control slave interface can be read back. Contents of registers 6 and above cannot be read back in any mode.
  • Added a note in the Gamma Corrector Control Registers section that the values written to registers 6 and above cannot be read back in any mode.
  • Updated the Memory Map for Frame Reader section with information about ancillary packets and edited the Memory Map for Base Address 0x1000_0000 for Non 8-Bit Pixel Values figure with the correct mapping.
  • Updated the Clocked Video Output II Control Registers section. Some minor changes were made to the common control registers to correct reported bugs and limitations.
  • Added a new register (Motion scale) to the Deinterlacer II Control Registers section.
  • Added information and changed the title of the Tuning Motion Shift section to .
May 2017 2017.05.10 Republished to add some missing chapters due to technical glitch.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Added preliminary device support for Intel® Cyclone® 10 LP and Intel® Cyclone® 10 GX devices.
  • Removed all information about the following IP cores. These IP cores are no longer supported in Intel® Quartus® Prime versions 17.0 and later.
    • 2D FIR Filter
    • Alpha Blending Mixer
    • Chroma Resampler
    • Color Space Converter
    • Color Plane Sequencer
    • Deinterlacer
    • Frame Buffer
    • Frame Reader
    • Gamma Corrector
    • Interlacer
    • Switch
  • Added information for the Configurable Guard Bands IP core. This is a new IP core being released in version 17.0.
  • Updated the performance and resource data information based on an Arria 10 device.
  • Updated the stall behavior and error recovery information for 2D FIR Filter II, CVO/CVO II, Color Plane Sequencer II, and Deinterlacer II IP cores.
  • Added or updated these chapters:
    • Clocked Video
    • VIP Run-Time Control
    • VIP Connectivity Interfacing
    • VIP Software Control
  • Reorganized the signals, parameters, and registers information according to the respective Clocked Video Interface IP cores.
  • Updated the description for the vid_color_encoding and vid_bit_width signals in the CVI II IP core. Tie these signals to low if no equivalent signals are available from the IP core driving the CVI II.
  • Updated GUI information for the Chroma Resampler II IP core. Added the following parameters:
    • Enable vertical luma adaptive resampling
    • Vertical chroma siting
    • Variable 3 color interface
    • Enable 4:2:0 input
    • Enable 4:2:0 output
  • Updated GUI information for the Deinterlacer II IP core.
    • Removed the How user packets are handled: Pass all user packets through to the output and Enable embedded chroma resamplers parameters.
    • Edited the description for the Deinterlacing algorithm, Fields buffered prior to output, and Use separate clock for the Avalon-MM master interface(s) parameters.
  • Changed Cadence Detect On register to Cadence Detect and advanced tuning registers On register for the Deinterlacer II IP core. This updated register enables the cadence detection feature and (if configured) the video over film feature together with all the motion and cadence/VOF tuning registers.
  • Updated the Scaler II calculation for the nearest neighbor algorithm.
  • Removed edge sharpening feature for the Scaler II IP core.
  • Clarified the GUI information for the Test Pattern Generator II IP core.
October 2016 2016.10.31
  • Added information about these new IP cores:
    • 2D FIR Filter II
    • Chroma Resampler II
    • Color Plane Sequencer II
    • Gamma Corrector II
    • Interlacer II
  • Added a flowchart to illustrate the behavior of the VIP IP cores.
  • Updated information for Deinterlacer II IP core (this IP core is now merged with the Broadcast Deinterlacer IP core).
    • Updated the Deinterlacer II parameter settings table to include the new parameters.
    • Added new information about Avalon-ST Video and 4K Video passthrough support.
    • Updated the Motion Adaptive mode bandwidth requirements to reflect the upgraded Deinterlacer II IP core.
  • Updated information for Clocked Video Output IP cores.
    • Updated mode bank selection information for CVO and CVO II IP cores. You can configure the IP cores to support 1 to 13 modes.
    • Added information to enable the Go bit for both CVO IP cores to avoid situations where a write in the streaming side cannot be issued to the video clock side because the video clock isn't running.
    • Added new parameter for CVO II IP core: Low latency mode. Setting this parameter to 1 enables the IP core to start timing for a new frame immediately
  • Updated information for Clocked Video Input II IP core.
    • Added three new parameters: Enable matching data packet to control by clipping, Enable matching data packet to control by padding, Overflow handling.
    • Added two new signals: Clipping and Padding.
    • Updated description for these signals: vid_color_encoding and vid_bit_width.
    • Updated information about the Status register. The register now includes bits to support clipping and padding features.
  • Updated information for Mixer II IP core.
    • Updated alpha stream information for Mixer II IP core. When you enable alpha stream, the LSB is in Alpha value and the control packets are composed of all symbols including Alpha.
    • Corrected the description for the Control and Status registers.
May 2016 2016.05.02
  • Added information about a new IP core: Avalon-ST Video Stream Cleaner.
  • Frame Buffer II IP core:
    • Added new Frame Buffer II IP core parameters:
      • Enable use of fixed inter-buffer offset
      • Inter-buffer offset
      • Module is Frame Reader only
      • Module is Frame Writer only
    • Updated the default values for these Frame Buffer II IP core parameters:
      • Maximum frame width = 1920
      • Maximum frame height = 1080
    • Updated the existing and added new Frame Buffer II IP core registers.
    • Added new information for Frame writer-only and Frame reader-only modes.
  • Broadcast Deinterlacer IP core:
    • Updated the existing and added new Broadcast Deinterlacer IP core registers.
    • Edited the Design Guidelines for Broadcast Deinterlacer IP Core section and removed the Active Video Threshold Adjustment section. The information is no longer relevant.
  • Clocked Video Interface IP core:
    • Added new or updated these Clocked Video Input II IP core signals:
      • dout_empty
      • vid_locked (updated)
      • vid_datavalid (updated)
      • vid_color_encoding
      • vid_bit_width
      • vid_total_sample_count
      • vid_total_line_count
    • Added a new register, Color Pattern, for the Clocked Video Input II IP core.
    • Updated information for the Standard format for the Clocked Video Input II IP core.
    • Added new information for output video modes in the Clocked Video Output II IP core.
    • Added information that multiple pixels in parallel are only supported for external sync mode in the Clocked Video Output II IP core.
    • Removed the Accept synchronization outputs parameter and the related signals from the Clocked Video Output II IP core.
      • vcoclk_div
      • sof
      • sof_locked
      • vid_sof
      • vid_sof_locked
  • Mixer II IP core:
    • Added new or updated the following Mixer II IP core parameters:
      • Number of inputs
      • Alpha Blending Enable
      • Layer Position Enable
      • Register Avalon-ST ready signals
      • Uniform values
      • Number of pixels transmitted in 1 clock cycle
      • Alpha Input Stream Enable
      • 4:2:2 support
      • How user packets are handled
    • Removed these Mixer II IP core parameters:
      • Number of color planes
      • Run-time control
      • Output format
    • Updated the existing and added new Mixer II IP core registers.
    • Added alpha blending information for Mixer II IP core in the Alpha Blending - Mixer II section.
    • Added information about defining layer mapping in the Layer Mapping- Mixer II section.
  • Switch II IP core:
    • Updated the features information to include that each input drives multiple outputs and each output is driven by one input.
    • Added a new register: Din Consume Mode Enable
  • Added links to archived versions of the Video and Image Processing Suite User Guide.
November 2015 2015.11.02
  • Removed information about the Clipper and Test Pattern Generator IP cores. These cores are no longer supported in versions 15.1 and later.
  • Changed instances of Quartus II to Intel® Quartus® Prime .
  • Edited the description of the vid_de signal for the Clocked Input II IP core—this signal is driven by the IP core to indicate the data lines are carrying active picture.
  • Added two new Mixer II IP core registers.
  • Added conditions for the Video Mixing IP cores; if these conditions are not met, then the Mixer behavior is undefined and the core is likely to lock up.
  • Edited the description of the Coeff-commit control register for the Color Space Converter II IP core. Writing a 1 to this location commits the writing of coefficient data.
May 2015 2015.05.04
  • Edited the description of the Input (0-3) Enable registers for the Mixer II IP core. The 1-bit registers are changed to 2-bit registers:
    • Set to bit 0 of the registers to display input 0.
    • Set to bit 1 of the registers to enable consume mode.
  • Edited the description of the Interrupt register to unused for the Color Space Converter II, Frame Buffer II (writer), and Test Pattern Generator II IP cores.
  • Edited the register information for the Switch II IP core:
    • Changed the description of the Interrupt register to state that bit 0 is the interrupt status bit.
    • Updated the description of the Control register to add that bit 1 of the register is the interrupt enable bit.
    • Edited the typo in address 15 of the Switch II IP core— Dout12 Output Control changed to Dout11 Output Control.
  • Edited the typos in the descriptions for Output Width and Output Height registers for the Test Pattern Generator IP cores.
  • Edited the parameter settings information for the Mixer II IP core.
    • Added description for new parameter Pattern which enables you to select the pattern for the background layer.
    • Removed information about Color planes transmitted in parallel . This feature is now default and internally handled through the hardware TCL file.
  • Edited the parameter settings information for the Frame Buffer II IP core.
    • Added descriptions for parameters that were not supported in the previous version: Maximum ancillary packets per frame, Interlace support, Locked rate support, Run-time writer control, andRun-time reader control
    • Removed information about Ready latency and Delay length (frames). These features are fixed to 1 and internally handled through the hardware TCL file.
  • Edited the parameter settings information for the Avalon-ST Video Monitor IP core.
    • Added description for new parameters: Color planes transmitted in parallel and Pixels in parallel.
    • Removed information about the Number of color planes in sequence parameter. You can specify whether to transmit the planes in parallel or in series using the Color planes transmitted in parallel parameter.
    • Added a note that the Capture video pixel data feature only functions if you specify the number of pixels transmitted in parallel to 1.
January 2015 2015.01.23
  • Added support for Arria 10 and MAX 10 devices. Arria 10 devices support only the following IP cores: Avalon-ST Video Monitor, Broadcast Deinterlacer, Clipper II, Clocked Video Input, Clocked Video Input II, Clocked Video Output, Clocked Video Output II, Color Space Converter II, Deinterlacer II, Frame Buffer II, Mixer II, Scaler II, Switch II, and Test Pattern Generator II.
  • Removed the Generate Display Port output parameter from the Clocked Video Output II IP core. This feature is now default and internally handled through the hardware TCL file.
  • Added description for a new signal for Clocked Video Input II IP core: vid_hdmi_duplication[3:0].
  • Added information for the missed out Coeff-commit control register for the Color Space Converter II IP core.
  • Edited the description for the Frame Buffer II parameters.
August 2014 14.0
  • Added new IP cores: Clocked Video Output II, Clocked Video Input II, Color Space Converter II, Mixer II, Frame Buffer II, Switch II, and Test Pattern Generator II.
  • Revised the performance and resource data for different configurations using Arria V and Cyclone V devices.
  • Added information about IP catalog and removed information about MegaWizard Plug-In Manager.
  • Updated bit 5 of the Status register as unused for the Clocked Video Input IP core.
  • Corrected the formula for adjusting the filter function’s phase for the Scaler II IP core.
  • Consolidated the latency information for all IP cores in the Overview chapter.
  • Consolidated the stall behavior and error recovery information for all IP cores in the Overview chapter.
  • Moved the 'Video Formats' section from Clocked Video Input and Output chapters to the Interfaces chapter.
February 2014 13.1
  • Added information on 4:2:2 support.
  • Added Design Guidelines section for the Broadcast Deinterlacer IP core.
  • Removed information about Arria GX, Cyclone, Cyclone II, Stratix, Stratix GX, Stratix II, Stratix II GX, and all HardCopy devices. Altera no longer supports these devices.
July 2013 13.0
  • Added new IP cores: Broadcast Deinterlacer and Clipper II
  • Removed Scaler IP core. This core is no longer supported in version 13.0 and later.
  • Added information about the Add data enable signal parameter and the vid_de signal for Clocked Video Input IP core.
April 2013 12.1.1 Added the following information for the Avalon-ST Video Monitor IP core.
  • Added description for packet visualization.
  • Added explanation for Capture Rate per 1000000 option for monitor settings.
  • Added Capture video pixel data parameter.
  • Added Control Bits entry to the register map.
January 2013 12.1
  • Added Deinterlacer II Sobel-Based HQ Mode information for the Deinterlacer II IP core.
  • Updated Table 1–17 to include latest Deinterlacer II IP core performance figures for Cyclone IV and Stratix V devices.
  • Edited the description of the rst signal for the Clocked Video Output IP core.
  • Added a note to explain that addresses 4, 5, and 6 in the Frame Buffer control register map are optional and visible only when the GUI option is checked.
  • Updated Table 23–4 to include the functionality of address 0 in the register map.
July 2012 12.0
  • Added new IP cores: Avalon-ST Video Monitor and Trace System.
  • Added information on the edge-adaptive scaling algorithm feature for the Scaler II IP core.
February 2012 11.1
  • Reorganized the user guide.
  • Added new appendixes: “Avalon-ST Video Verification IP Suite” and “Choosing the Correct Deinterlacer”.
  • Updated Table 1-1 and Table 1-3.
May 2011 11.0
  • Added new IP core: Deinterlacer II.
  • Added new polyphase calculation method for Scaler II IP core.
  • Final support for Arria II GX, Arria II GZ, and Stratix V devices.
January 2011 10.1
  • Added new IP core: Scaler II.
  • Updated the performance figures for Cyclone IV GX and Stratix V devices.
July 2010 10.0
  • Preliminary support for Stratix V devices.
  • Added new IP core: Interlacer.
  • Updated Clocked Video Output and Clocked Video Input IP cores to insert and extract ancillary packets.
November 2009 9.1
  • Added new IP cores: Frame Reader, Control Synchronizer, and Switch.
  • The Frame Buffer IP core supports controlled frame dropping or repeating to keep the input and output frame rates locked together. The IP core also supports buffering of interlaced video streams.
  • The Clipper, Frame Buffer, and Color Plane Sequencer IP cores now support four channels in parallel.
  • The Deinterlacer IP core supports a new 4:2:2 motion-adaptive mode and an option to align read/write bursts on burst boundaries.
  • The Line Buffer Compiler IP core has been obsoleted.
  • The Interfaces chapter has been re-written.
March 2009 8.0
  • The Deinterlacer IP core supports controlled frame dropping or repeating to keep the input and output frame rates locked together.
  • The Test Pattern Generator IP core can generate a user-specified constant color that can be used as a uniform background.
  • Preliminary support for Arria II GX devices.
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