A.2.5. Verification Files

Video and Image Processing Suite User Guide

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Date 4/04/2022

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A.2.5. Verification Files

You can use the verification files used for this example as templates for your designs.

Table 90. Verification File Folders
Folder	File	Description
class_library	av_mm_class.sv av_mm_control_bfm_class.sv av_mm_control_classes.sv av_mm_master_bfm_class_inc.sv av_mm_slave_bfm_class_inc.sv av_mm_split_rw_bfm_driver_fnc.sv av_st_control_bfm_class.sv av_st_video_classes.sv av_st_video_file_io_class.sv av_st_video_sink_bfm_class.sv av_st_video_source_bfm_class.sv tasks.sv warning_banners.sv	The class library files contain all the systemVerilog classes plus tasks to service Avalon-MM memory requests and to read and write video to file.
dut	dut.qsys	The DUT in the examples is a Platform Designer system which instances the Mixer II and Frame Buffer II IP cores.
example_constrained_random	run.tcl test.sv	Both the constrained random and video file examples run in the same way, using a simple run.tcl script and test.sv file.
example_video_files	jimP_rgb32.raw jimP_rgb32.spc	Test input video.
example_video_files	run.tcl test.sv	Both the constrained random and video file examples run in the same way, using a simple run.tcl script and test.sv file.
testbench	bfm_drivers.sv	bfm_drivers.sv links the class library to the BFMs in testbench.qsys.
	defines.sv	Edit defines.sv to vary quantities such as the number of pixels in parallel and the latency on the Avalon ST bus.
	nios_control_model.sv	CSR accesses to the VIP cores in the DUT are made using nios_control_model.sv in the same way that a Nios processor would in hardware.
	run.tcl	run.tcl is called by both tests. Edit for other simulators if needed.
	testbench.qsys	testbench.qsys instances dut.qsys together with a BFM for every Avalon-ST and Avalon-MM interface.
	testbench_stimulus.sv	testbench_stimulus.sv instances a testbench.v file (created when Platform Designer generates a simulation model from testbench.qsys) and includes all the other test files required. It is the top level of hierarchy in the simulations.