Intel Acceleration Stack Quick Start Guide: Intel FPGA Programmable Acceleration Card D5005

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ID 683394
Date 7/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements and Release Installation 3. Installing the OPAE Software Package 4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version 5. Running FPGA Diagnostics 6. Running the OPAE in a Non-Virtualized Environment 7. Running the OPAE in a Virtualized Environment 8. Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005 Archives 9. Document Revision History for Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005 A. Handling Graceful Thermal Shutdown B. FPGA Device Access Permission C. Memlock Limit D. Troubleshooting Frequently Asked Questions (FAQ)
2. System Requirements and Release Installation x
2.1. Unpacking the Intel® FPGA PAC 2.2. Precautions for Hardware Installation 2.3. Hardware Installation 2.4. Setting Up the Host Machine Software
2.4. Setting Up the Host Machine Software x
2.4.1. Installing Red Hat* Enterprise Linux* version 7.6 2.4.2. Installing the Intel Acceleration Stack 2.4.3. Verifying the Installation
2.4.2. Installing the Intel Acceleration Stack x
2.4.2.1. Installing the Intel Acceleration Stack Runtime Package on the Host Machine 2.4.2.2. Installing the Intel Acceleration Stack Development Package on the Host Machine
3. Installing the OPAE Software Package x
3.1. Unpacking and Installing the Intel FPGA Driver and the OPAE Software Development Kit (SDK) 3.2. Installing the PACSign
4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version x
4.1. Updating the FIM and BMC
4.1. Updating the FIM and BMC x
4.1.1. Updating the FIM and BMC using the fpgaotsu
6. Running the OPAE in a Non-Virtualized Environment x
6.1. Loading an AFU Image into the FPGA 6.2. Running the Hello FPGA Example
7. Running the OPAE in a Virtualized Environment x
7.1. Updating Settings Required for VFs 7.2. Configuring the VF Port on the Host 7.3. Running the Hello FPGA Example on Virtual Machine 7.4. Disconnecting the VF from the VM and Reconnecting to the PF
D. Troubleshooting Frequently Asked Questions (FAQ) x
D.1. Why do I see a 'No Suitable slots found' message when running fpgasupdate on my AFU image? D.2. Which environment variables are required? D.3. What actions do I take if I see the error message 'Error enumerating resources: no driver available'? D.4. Command lsmod | grep fpga shows no output after installing the OPAE driver. How to successfully install the OPAE driver? D.5. Command rpm -qa | grep opae does not return the installed opae rpm package. How to successfully install the packages? D.6. What action do I take if the Intel® FPGA PAC D5005 does not show up on the PCIe bus? D.7. Why does the PCIe not detect the Intel® FPGA PAC D5005 card?
1. About this Document
2. System Requirements and Release Installation
3. Installing the OPAE Software Package
4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version
5. Running FPGA Diagnostics
6. Running the OPAE in a Non-Virtualized Environment
7. Running the OPAE in a Virtualized Environment
8. Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005 Archives
9. Document Revision History for Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005
A. Handling Graceful Thermal Shutdown
B. FPGA Device Access Permission
C. Memlock Limit
D. Troubleshooting Frequently Asked Questions (FAQ)

7. Running the OPAE in a Virtualized Environment

In SR-IOV mode, a host processor uses a physical function (PF) to access management functions. A virtual machine (VM) uses a virtual function (VF) to access the AFU.
Note: Partial reconfiguration (PR) is not available in this mode.
Figure 5. OPAE Driver in SR-IOV Mode

An application running in a virtual machine that connects to a VF through OPAE cannot initiate partial reconfiguration. The permission table in the FME enforces this restriction. The permission table only allows partial reconfiguration through a PF. Consequently, you must load the AFU image on the host before continuing with the steps to create a virtualized environment.

Run the following command on the host to load the AFU image on a board with no root entry hash programmed. 

sudo fpgasupdate \
$OPAE_PLATFORM_ROOT/hw/samples/nlb_mode_0/bin/nlb_mode_0_unsigned.gbs

Section Content
Updating Settings Required for VFs
Configuring the VF Port on the Host
Running the Hello FPGA Example on Virtual Machine
Disconnecting the VF from the VM and Reconnecting to the PF

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