Intel Acceleration Stack Quick Start Guide: Intel FPGA Programmable Acceleration Card D5005

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ID 683394
Date 7/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements and Release Installation 3. Installing the OPAE Software Package 4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version 5. Running FPGA Diagnostics 6. Running the OPAE in a Non-Virtualized Environment 7. Running the OPAE in a Virtualized Environment 8. Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005 Archives 9. Document Revision History for Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005 A. Handling Graceful Thermal Shutdown B. FPGA Device Access Permission C. Memlock Limit D. Troubleshooting Frequently Asked Questions (FAQ)
2. System Requirements and Release Installation x
2.1. Unpacking the Intel® FPGA PAC 2.2. Precautions for Hardware Installation 2.3. Hardware Installation 2.4. Setting Up the Host Machine Software
2.4. Setting Up the Host Machine Software x
2.4.1. Installing Red Hat* Enterprise Linux* version 7.6 2.4.2. Installing the Intel Acceleration Stack 2.4.3. Verifying the Installation
2.4.2. Installing the Intel Acceleration Stack x
2.4.2.1. Installing the Intel Acceleration Stack Runtime Package on the Host Machine 2.4.2.2. Installing the Intel Acceleration Stack Development Package on the Host Machine
3. Installing the OPAE Software Package x
3.1. Unpacking and Installing the Intel FPGA Driver and the OPAE Software Development Kit (SDK) 3.2. Installing the PACSign
4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version x
4.1. Updating the FIM and BMC
4.1. Updating the FIM and BMC x
4.1.1. Updating the FIM and BMC using the fpgaotsu
6. Running the OPAE in a Non-Virtualized Environment x
6.1. Loading an AFU Image into the FPGA 6.2. Running the Hello FPGA Example
7. Running the OPAE in a Virtualized Environment x
7.1. Updating Settings Required for VFs 7.2. Configuring the VF Port on the Host 7.3. Running the Hello FPGA Example on Virtual Machine 7.4. Disconnecting the VF from the VM and Reconnecting to the PF
D. Troubleshooting Frequently Asked Questions (FAQ) x
D.1. Why do I see a 'No Suitable slots found' message when running fpgasupdate on my AFU image? D.2. Which environment variables are required? D.3. What actions do I take if I see the error message 'Error enumerating resources: no driver available'? D.4. Command lsmod | grep fpga shows no output after installing the OPAE driver. How to successfully install the OPAE driver? D.5. Command rpm -qa | grep opae does not return the installed opae rpm package. How to successfully install the packages? D.6. What action do I take if the Intel® FPGA PAC D5005 does not show up on the PCIe bus? D.7. Why does the PCIe not detect the Intel® FPGA PAC D5005 card?
1. About this Document
2. System Requirements and Release Installation
3. Installing the OPAE Software Package
4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version
5. Running FPGA Diagnostics
6. Running the OPAE in a Non-Virtualized Environment
7. Running the OPAE in a Virtualized Environment
8. Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005 Archives
9. Document Revision History for Intel® Acceleration Stack Quick Start Guide: Intel® FPGA PAC D5005
A. Handling Graceful Thermal Shutdown
B. FPGA Device Access Permission
C. Memlock Limit
D. Troubleshooting Frequently Asked Questions (FAQ)

6.1. Loading an AFU Image into the FPGA

You can utilize the fpgasupdate utility to load an AFU image. In Acceleration Stack 2.0.1 and later versions, the Intel® FPGA PAC must be programmed with AFU images that have been prepended with mandatory headers. These headers are applied by the PACSign tool. For more information on the PACSign tool, please refer to the Security User Guide: Intel FPGA Programmable Acceleration Card D5005.

The samples included with Acceleration Stack have been processed by PACSign and the AFU binary files are located at: 
$OPAE_PLATFORM_ROOT/hw/samples/<AFU Name>/bin/*_unsigned.gbs

If the Intel® FPGA PAC is programmed with a root entry hash following the steps in the Security User Guide: Intel FPGA Programmable Acceleration Card D5005, then the provided AFU bitstreams (for example: hello_afu_unsigned.gbs) must be signed using PACSign with the appropriate root and code signing keys before you can successfully program the signed AFU bitstream. 

sudo fpgasupdate <AFU image>

The fpgasupdate tool can program an unsigned AFU bitstream provided that there is no root entry hash programmed into the flash.

The fpgasupdate tool also accepts PCIe* Bus:Device:Function (BDF) as an additional optional argument if multiple cards are connected to the server. Use the help text (-h) to see how additional arguments must be passed. For example: sudo fpgasupdate -h.

To identify the BDF run the following command: 

 lspci | grep 0b2b

Sample output:

37:00.0 Processing accelerators: Intel Corporation Device 0b2b (rev 01)

In the Sample Output, the PCIe Bus is 0x37, the Device is 0x00, and the Function is 0x0.

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