AN 747: Implementing PHYLite in Intel® Arria® 10 Devices Design Examples

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ID 683384
Date 5/08/2017
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Document Table of Contents
Document Table of Contents x
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note x
1.1. Simple Input/Output PHYLite Simulation Design Example 1.2. Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware Reference Design 1.3. Functional Description 1.4. Document Revision History
1.1. Simple Input/Output PHYLite Simulation Design Example x
1.1.1. Simulation Design Example Architecture 1.1.2. Simulation Reference Design User Guide 1.1.3. Result
1.1.2. Simulation Reference Design User Guide x
1.1.2.1. Requirements 1.1.2.2. Setting Up the Simulation Environment 1.1.2.3. Running Simulation
1.2. Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware Reference Design x
1.2.1. Hardware Reference Design Architecture 1.2.2. Hardware Design Example User Guide 1.2.3. Result
1.2.2. Hardware Design Example User Guide x
1.2.2.1. System Requirements 1.2.2.2. Setting Up the Development Kit 1.2.2.3. Generating Executable and Linking Format (.elf) Programming File 1.2.2.4. Running the Hardware Reference Design
1.2.3. Result x
1.2.3.1. Dynamic Calibration Result 1.2.3.2. Random Data Transfer Result
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note

1.1.2.2. Setting Up the Simulation Environment

  1. Follow the guidelines in Getting Started with the Design Store to download and install the reference design files.
  2. Open the reference design .qpf file after successfully installing the design templates.
  3. Click on Assignments -> Settings....
  4. Select EDA Tools Settings -> Simulation.
  5. At the Settings window, choose ModelSim* - Intel® FPGA Edition for Tool Name. You may choose VHDL, Verilog HDL or System Verilog as the output netlist format.
    Figure 2. Simulation Settings using EDA Tools in the Intel® Quartus® Prime Software
  6. Open dut_INPUT.qsys file and make sure the IP has the same configuration shown below:
    Figure 3. Configuration for dut_INPUT Module
  7. Make sure that the Capture strobe phase shift is set to 0 degrees to align the incoming data to strobe edge during data transfer.
  8. Click Generate HDL... and select your desired simulation model format. Next, click Generate to generate the simulation model for the dut_INPUT module. Click Close and Finish when the generation is complete.
    Figure 4. Generating Simulation Model
  9. From the Intel® Quartus® Prime software, open dut_OUTPUT.qsys file and make sure the IP has the same configuration shown below:
    Figure 5. Configuration for dut_OUTPUT Module
  10. Make sure the Output strobe phase is set to 0 degrees to align outgoing data with strobe edge during data transfer.
  11. Repeat step 9 to generate simulation model for dut_OUTPUT module.
  12. From the Intel® Quartus® Prime software, click Processing > Start > Start Analysis & Elaboration to compile the design.
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