1.3. Functional Description
Device Under Test (DUT) Module
The DUT module consists of two Altera PHYLite IP instances:
- 4-bit dut_INPUT module
- 4-bit dut_OUTPUT module
The function of the dut_INPUT module is to:
- Receives data aligned to strobe edge from external I/O interface.
- Receives rdata_en signal from traffic generator.
- Transmits data from external I/O interface to the traffic generator.
The function of dut_OUTPUT is to:
- Receives data, strobe, and output enable from the traffic generator.
- Transmits edge aligned data and strobe to external I/O interface.
The DUT module in the hardware reference design also consists of a PHYLite Avalon Controller. The functions of the PHYLite Avalon controller includes:
- To perform address translation for each reconfigurable feature of the PHYLite IP.
- To cache all necessary settings for each reconfigurable feature of the PHYLite IP.
- To translate Nios II soft processor commands into PHYLite commands.
Traffic Generator
The traffic generator module is called tg and is located in the tg.v file.
The functionality of the traffic generator includes:
- Continuously generates data to dut_OUTPUT module through Linear Feedback Shift Register.
- Asserts rdata_en signal to dut_INPUT module to read the loopback data from dut_OUTPUT module.
- Compares received data against the regenerated/transmitted data.
- Increments correct_data_counter for every correct data received. The correct_data_counter is a 15-bit counter.
- Asserts the done signal to indicate all data has completely received correctly.
In the hardware design example, the traffic generator sends out loopback data for comparison after NIOS II processor completes the calibration process.
NIOS II Soft Processor
The Nios II soft processor calibrates read and write operations. The Nios II interfaces with the DUT module through the Avalon Controller.
Dummy PHYLite
Due to the limitation of the Arria 10 development board, this module is required to enable the design example to connect a reference clock to the DUT module data pins.
In-System Sources and Probes (altsource_probe) Module
This module is an in-system debugging IP. You can use this module to drive and capture the behavior of the internal signals in the design example. This module is only used in the hardware design example.
Design Example Software
The hardware design example requires hello_world.c, phylite_dynamic_reconfiguration.c and phylite_dynamic_reconfiguration.h files to run.
The hello_world.c file function is to identify the strobe enable window. The phylite_dynamic_reconfiguration.c and phylite_dynamic_reconfiguration.h are the library files used by hello_world.c file. The find_strobe_enable_window() function in the hello_world.c performs calibration algorithm as follow:
- Read the initial output strobe phase from ODELAY CSR.
- Configure and update new output strobe phase delay.
- Verify the new output strobe phase delay with test data.
- Sweep across a range of output strobe phase delays to identify valid strobe capture window.
- Find the center output strobe phase from the valid strobe capture window.
You can configure the delay for DQS, DQ[0] and DQ[1] values to achieve better results. This reference design, configures only the DQS value.