Visible to Intel only — GUID: suc1432748243108
Ixiasoft
Visible to Intel only — GUID: suc1432748243108
Ixiasoft
1.1.1.5. SPI Slave Output Signals Cannot Be Isolated When Routed to the HPS Pins
Description
The SPI output enable is not connected to the SPI HPS pins. Because of this error, the peripheral cannot isolate itself from the SPI bus when routed to the HPS pins. As a result, the HPS SPIS_TXD pin cannot be tri-stated by setting the slv_oe bit (bit 10) in the ctrlr0 register to 1.
Workaround
Route the SPI slave signals to the FPGA fabric. Because the output enable signal is exposed through the FPGA fabric, you can connect it to an FPGA tri-state pin and enable tri-stating when necessary.
Status
Affects: All Arria® V SX and ST devices
Status: No planned fix