Visible to Intel only — GUID: suc1422638695813
Ixiasoft
1.1.1.1. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric
1.1.1.2. Hard Processor System Level 2 Cache Error Correction Code
1.1.1.3. Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset
1.1.1.4. HPS TAP Controller Is Reset By Cold Reset
1.1.1.5. SPI Slave Output Signals Cannot Be Isolated When Routed to the HPS Pins
1.2.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain
1.2.1.2. 775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock
1.2.1.3. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock
1.2.1.4. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock
1.2.1.5. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
1.2.1.6. 740657: Global Timer Can Send Two Interrupts for the Same Event
1.2.1.7. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary
1.2.1.8. 754322: Faulty MMU Translations Following ASID Switch
1.2.1.9. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory
1.2.1.10. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault
1.2.1.11. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation
1.2.1.12. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements
1.2.1.13. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue
1.2.1.14. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D
1.2.1.15. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface
1.2.1.16. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded
1.2.1.17. 751471: DBGPCSR Format Is Incorrect
1.2.1.18. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads
1.2.1.19. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store
1.2.1.20. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses
1.2.1.21. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP
1.2.1.22. 761321: MRC and MCR Are Not Counted in Event 0x68
1.2.1.23. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF
1.2.1.24. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value
1.2.1.25. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB
1.2.1.26. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock
1.2.1.27. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
1.2.1.28. 782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region
1.2.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area
1.2.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23
1.2.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
Visible to Intel only — GUID: suc1422638695813
Ixiasoft
1.2.1. Arm* Cortex* -A9 MPU
Section Content
761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain
775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock
782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock
761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock
845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
740657: Global Timer Can Send Two Interrupts for the Same Event
751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary
754322: Faulty MMU Translations Following ASID Switch
764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory
782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault
794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation
794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements
794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue
725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D
729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface
729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded
751471: DBGPCSR Format Is Incorrect
752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads
754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store
756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses
757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP
761321: MRC and MCR Are Not Counted in Event 0x68
764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF
771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value
771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB
771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock
775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region