Arria® V SX and ST SoC Errata

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ID 683370
Date 7/14/2015
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Document Table of Contents x
1. Arria® V SX and ST SoC Errata
1. Arria® V SX and ST SoC Errata x
1.1. Altera-Specific SoC Errata for Arria® V SX and ST Devices 1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata 1.3. Revision History for Arria® V SX and ST SoC Errata
1.1. Altera-Specific SoC Errata for Arria® V SX and ST Devices x
1.1.1. Hard Processor System (HPS) 1.1.2. FPGA
1.1.1. Hard Processor System (HPS) x
1.1.1.1. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric Description Workaround Status 1.1.1.2. Hard Processor System Level 2 Cache Error Correction Code 1.1.1.3. Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset 1.1.1.4. HPS TAP Controller Is Reset By Cold Reset 1.1.1.5. SPI Slave Output Signals Cannot Be Isolated When Routed to the HPS Pins
1.1.2. FPGA x
1.1.2.1. False Configuration Failure in Active Serial Multi-Device Configurations
1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata x
1.2.1. Arm* Cortex* -A9 MPU 1.2.2. Arm* L2 Cache Controller 1.2.3. Arm* CoreSight PTM
1.2.1. Arm* Cortex* -A9 MPU x
1.2.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 1.2.1.2. 775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock 1.2.1.3. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock 1.2.1.4. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock 1.2.1.5. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 1.2.1.6. 740657: Global Timer Can Send Two Interrupts for the Same Event 1.2.1.7. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 1.2.1.8. 754322: Faulty MMU Translations Following ASID Switch 1.2.1.9. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory 1.2.1.10. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault 1.2.1.11. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 1.2.1.12. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 1.2.1.13. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue 1.2.1.14. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 1.2.1.15. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 1.2.1.16. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 1.2.1.17. 751471: DBGPCSR Format Is Incorrect 1.2.1.18. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 1.2.1.19. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 1.2.1.20. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 1.2.1.21. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 1.2.1.22. 761321: MRC and MCR Are Not Counted in Event 0x68 1.2.1.23. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 1.2.1.24. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value 1.2.1.25. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 1.2.1.26. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock 1.2.1.27. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back 1.2.1.28. 782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region
1.2.2. Arm* L2 Cache Controller x
1.2.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 1.2.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 1.2.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
1.2.3. Arm* CoreSight PTM x
1.2.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 1.2.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. Arria® V SX and ST SoC Errata

1.1.1.1. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric

Description

The default setting of the physel_x field in the System Manager EMAC Control Group's ctrl register cannot be used to configure an HPS I/O RMII PHY interface. Because the HPS I/O timings do not support RMII protocol, encodings 0x0 and 0x1 are the only valid values in the physel_x field. Selecting the 0x0 encoding routes the GMII/MII signals to the FPGA fabric only, and selecting the 0x1 encoding routes the RGMII interface to the HPS I/O only. If the physel_x encoding is left as 0x2, the HPS PHY interface does not function properly.

Workaround

If an RMII PHY interface is required, the physel_x field should be set to 0x0 so that the GMII/MII signals are routed to the FPGA. You can design an RMII soft adaptor in the FPGA configuration file that converts these MII signals to an RMII PHY interface that is mapped to the FPGA I/O pins. Refer to the “Programming Model” section of the EMAC chapter in the Volume 3: Hard Processor System Technical Reference Manual for more information about how to initialize the EMAC Controller and interface.

Status

Affects: All Arria® V SX and ST devices

Status: No planned fix

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