SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

Download PDF
ID 683368
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

2.6. Video Pattern Generator Parameters

Customize the video pattern generator parameters according to your design.
Table 19.   Video Pattern Generator Parameters
Parameter Valid Value Default Value Description

OUTW_MULTP

1, 4

1

Defines the width of the output ports. Select 4 for a multi-rate design, otherwise select 1.

SD_BIT_WIDTH

10, 20

10

Defines the generated SD interface bit width. This value must match with the SD interface bit width parameter of the SDI II TX core in the same design.

TEST_GEN_ANC

0, 1

0

Select 1 to generate the ancillary data packet in output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled.

TEST_GEN_VPID

0, 1

0

Select 1 to generate the payload ID packet in output streams. The module inserts the embedded Data ID (DID) packet with 10’h241.

Level Two Title