SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

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ID 683368
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

1.6. SDI II Intel® FPGA Design Example Parameters

Table 9.   SDI II Intel® FPGA Design Example Parameters for Intel® Stratix® 10 Devices

Parameter

Value

Description

Available Design Example
Select Design

Parallel loopback with external VCXO,

Parallel loopback without external VCXO,

Serial loopback

 Select the design example to be generated.
  • Parallel loopback with external VCXO: Parallel loopback design with an external VCXO to synchronize the clock between RX and TX.
  • Parallel loopback without external VCXO: Parallel loopback design which uses internal fPLL on the FPGA to synchronize the clock between RX and TX. Each independent channel requires a dedicated fPLL on the transceiver bank to operate on its own. Intel recommends you to place the reference clock pin to the fPLL near the respective fPLL and do not cross the reference clock pin to the neighboring transceiver bank.
    Note: This option is only available if you use production device.
  • Serial loopback: A serial loopback design to enables a simple demonstration when you do not have a video source available and to highlight the Dynamic Tx clock switching feature. The IP core generates an internal video pattern generator along with the TX to be transmitted to RX.
Design Example Options

TX PLL type

CMU,

fPLL,

ATX

ATX-fPLL cascading

Select the transceiver PLL type.

  • CMU PLL only supports data rates up to 3G-SDI.
    Note: Not applicable for parallel loopback designs without an external VCXO.
  • fPLL supports all data rates up to 12G-SDI.
    Note: Only fPLL is available when you generate a parallel loopback design without an external VCXO in single or triple-rate mode.
  • ATX supports all data rates up to 12G-SDI.
    Note: Not applicable for parallel loopback designs without an external VCXO.
  • ATX-fPLL cascading is available only when you select parallel loopback without external VCXO design example in multi-rate (up to 12G-SDI) mode.

Dynamic TX clock switching

Off,

Tx PLL switching,

Tx PLL reference clock switching
  • Off: Disable dynamic switching.
  • TX PLL switching: Instantiates two PLLs, each with its own reference input clock.
  • TX PLL reference clock switching: Instantiates one PLL with two reference input clocks.

Turn on this option to allow dynamic switching between 1 and 1/1.001 data rates.

Design Example Files
Simulation

On,

Off

Turn on this option to generate the necessary files for the simulation testbench.
Synthesis

On,

Off

 Turn on this option to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration.

Generated HDL Format
Generate File Format

Verilog,

VHDL

 Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.

Target Development Kit

Select Daughter Card

Nextera VIDIO 12G-SDI FMC card,

Terasic 12G-SDI FMC card

 Select the daughter card to be paired with the Intel FPGA development kit you select for the Select Board parameter. The design example is configured to utilize the on-board SDI connectors when this option is grayed out. This option is not valid when you select the No Development Kit or Custom Development Kit parameter.
Select Board

No Development Kit,

Stratix 10 GX FPGA L-tile Development Kit,

Stratix 10 GX FPGA H-tile Development Kit,

Custom Development Kit

 Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Intel® Stratix® 10 L-tile or H-tile FPGA Development Kit: This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit. Based on the Intel® Stratix® 10 device you are using, you can choose to use either the Stratix 10 GX FPGA L-tile or H-tile development kit.
    Note: This option is not available if you select Bidirectional mode. The SDI channels on the development kit and daughter card pins are only compatible with simplex mode.
  • Custom Development Kit: This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device

On,

Off

 Turn on this option and select the preferred device variant for the development kit.
Level Two Title