SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

Download PDF
ID 683368
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version Intel® FPGA IP Version Changes
2022.03.28 21.4 19.2.0 Updated Select Design parameter description for Parallel loopback without external VCXO in SDI II Intel FPGA Design Example Parameters for Intel Stratix 10 Devices table.
2021.10.08 21.3 19.1.1
  • Removed NCSim from the following figure and tables:
    • Figure: Directory Structure for the Design Examples.
    • Table: Other Generated Files in Simulation Folder.
    • Table: Steps to Run Simulation
  • Edited the list of Software in Hardware and Software Requirements:
    • Changed ModelSim* - Intel® FPGA Edition to Questa*-Intel® FPGA Edition .
    • Changed ModelSim* - Intel® FPGA Starter Edition to ModelSim SE* .
2021.08.27 20.3 19.1.1
  • Changed from Streams Interleaved to Multiplex Type to align with SMPTE spec for below:
    • RX/TX/DU Top Signals Table for rx_vid_std, tx_vid_std and sdi_tx_ln_b signals.
    • On-board User LED Functions Table.
    • Figure Sequence of Video Standards for Triple-Rate and Multi-Rate Designs.
    • Description in Simulation Testbench for single-rate and multi-rate designs.
2020.10.05 20.3 19.1.1
  • Added a note regarding transceiver reference clock pin due to the limitation on transceiver reference clock pin connection to the core logic in specific channels in a transceiver bank for the following signals:
    • rx_core_refclk
    • rx_rcfg_mgmt_clk
    • tx_rcfg_mgmt_clk
    • sdi_reclk_sysclk
    • clk in the Transceiver Arbiter module
  • Added Upgrading Your Design section.
2020.02.25 19.2 19.1.1 Edited the note in the description for the Select Board parameter in the Design Example Parameters section. This parameter is not applicable for any designs in Bidirectional mode.
2019.07.30 19.2 19.1.1
  • Updated the Directory Structure section to include the following files and folder:
    • alt_reset_delay.v
    • device_init.v
    • reset_release.ip
    • <reset release ip generated folder>
  • Added the device initialization module in the block diagrams in the SDI II Intel® FPGA IP Design Example Detailed Description chapter.
  • Added information about the device initialization module in the Design Components section.
  • Updated the description for tx_rcfg_mgmt_clk and rx_rcfg_mgmt_clk clocks in the Clocking Scheme Signals section to include that these signals also clock the reset delay block in the device initialization module.
  • Added information about the device initialization signals in the Interface Signals section.
2019.04.01 19.1 –
  • Edited all the parallel and serial loopback serial and parallel design example block diagrams to include the TX reconfiguration management block in the Parallel Loopback Design Examples, Serial Loopback Design Examples, and Simulation Testbench sections.
  • Added Terasic 12G-SDI FMC daughter card in the Hardware and Software Requirements section. This daughter card is required if your design targets an Intel® Stratix® 10 L-tile device.
  • Updated the steps for specifying the clock controller settings and programing the device in the Compiling and Testing the Design section.
  • Updated the guidelines about the connections and settings for multi-rate designs in the Connections and Settings Guidelines section to include information about the Terasic 12G-SDI FMC daughter card.
  • Added support for parallel loopback without external VCXO designs for multi-rate modes. This option is available only in Intel® Stratix® 10 H-tile and L-tile production devices.
  • Added option for Intel® Stratix® 10 L-tile development kit and a new parameter for selecting daughter card. The Select Daughter Card parameter enables you to choose either Nextera or Terasic daughter card for certain design variants.
  • Added PLL information for parallel loopback without external VCXO multi-rate designs in the Design Components section. The design example provides an ATX-fPLL cascading configuration for optimal jitter performance.
  • Updated the description about TX Refclock and TX Alt Refclock in the Clocking Scheme Signals section. Added a note that for 12G-SDI designs, Intel recommends to place the refclk pin within the same transceiver bank as the TX PLL block to ensure optimal jitter performance in your design.
  • Added description for a new input signal, gxb_tx_ready, in the Interface Signals section. This reset signal indicates that TX is ready to receive.
  • Edited the description for the tx_pll_refclk_sel signal in the Interface Signals section to include information about the dynamic switching feature.
  • Added description for sdi_refclk_sma_p in the Interface Signals section. This signal is a dedicated transceiver reference clock that is connected to the second TX PLL in parallel loopback designs with dynamic TX clock switching enabled.
  • Added description for the Terasic SDI FMC daughter card pins on FMC port A in the Interface Signals section.
2018.05.07 18.0 –
  • Renamed Intel FPGA SDI II IP core to SDI II Intel® FPGA IP core as part of standardizing and rebranding exercise.
  • Renamed hard transceiver to Native PHY IP for better clarity.
  • Added information about the newly added Parallel loopback without external VCXO design option. This option is now available for Intel® Stratix® 10 designs. Only fPLL is applicable with this option.
  • Updated the Directory Structure section with new folders and files for loopback design and simulation:
    • sdi_reclock.v
    • pid_controller.v
    • rcfg_pll_frac.v
    • modelsim_files.tcl
    • ncsim_files.tcl
    • riviera_files.tcl
    • vcs_files.tcl
    • vcsmx_files.tcl
    • xcelium_files.tcl
    • tb_ln_check.v
    • cds.lib
    • hdl.var
    • xcelium_setup.sh
    • xcelium_sim.sh
  • Added a note that fPLL is only available when you select the Parallel loopback without external VCXO design.
  • Added information that the multi-rate designs support rx_coreclk frequency of 297 MHz.
  • Added instructions to run simulation using the Xcelium* Parallel Simulator in the Simulating the Design section.
  • Edited the Hardware and Software Requirements section to include the Xcelium* Parallel simulator.
  • Added the 125-MHz clock signal (clk_enet) in the Interface Signals section.
  • Updated description for refclk_qsfp1_p. The signal is programmable to 148.5, 148.35165, or 100 MHz from the Clock Controller.
  • Edited the design example block diagrams to remove an incorrect data connection.
2017.11.06 17.1 – Initial release.
Level Two Title