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Ixiasoft
Visible to Intel only — GUID: gof1481302624250
Ixiasoft
1.2. Overview of HPS Design Guidelines for SoC FPGA design
Stages of the HPS Design Flow |
Guidelines |
Links |
---|---|---|
Hardware and Software Partitioning |
Determine your system topology and use it as a starting point for your HPS to FPGA interface design. |
Guidelines for Interconnecting the HPS and FPGA |
HPS Pin Multiplexing and I/O Configuration Settings |
Plan configuration settings for the HPS system including I/O multiplexing options, interface to FPGA and SDRAM, clocks, peripheral settings |
Design Considerations for Connecting Device I/O to HPS Peripherals and Memory |
HPS Clocks and Reset Considerations |
HPS clocks and cold and warm reset considerations |
HPS Clocking and Reset Design Considerations |
HPS EMIF Considerations |
Usage of the HPS EMIF controller and related considerations |
HPS EMIF Design Considerations |
FPGA Accelerator Design Considerations |
Design considerations to manage coherency between FPGA accelerators and the HPS |
DMA Considerations |
Recommended Tools for IP Development |
Signal Tap II, BFMs, System Console |
IP Debug Tools |