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1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
2. Background: Comparison between Cyclone® V SoC FPGA and Arria® V SoC FPGA HPS Subsystems
3. Design Guidelines for HPS portion of SoC FPGAs
4. Board Design Guidelines for SoC FPGAs
5. Embedded Software Design Guidelines for SoC FPGAs
A. Support and Documentation
B. Additional Information
4.2.1.1. Boot Source
4.2.1.2. Select Desired Flash Device
4.2.1.3. BSEL Options
4.2.1.4. Boot Clock
4.2.1.5. CSEL Options
4.2.1.6. Selecting NAND Flash Devices
4.2.1.7. Determine Flash Programming Method
4.2.1.8. For QSPI and SD/MMC/eMMC Provide Flash Memory Reset
4.2.1.9. Selecting QSPI Flash Devices
4.5.1. HPS EMAC PHY Interfaces
4.5.2. USB Interface Design Guidelines
4.5.3. QSPI Flash Interface Design Guidelines
4.5.4. SD/MMC and eMMC Card Interface Design Guidelines
4.5.5. NAND Flash Interface Design Guidelines
4.5.6. UART Interface Design Guidelines
4.5.7. I2C Interface Design Guidelines
4.5.8. SPI Interface Design Guidelines
5.1.1. Assembling the Components of Your Software Development Platform
5.1.2. Selecting an Operating System for Your Application
5.1.3. Assembling your Software Development Platform for Linux
5.1.4. Assembling a Software Development Platform for a Bare-Metal Application
5.1.5. Assembling your Software Development Platform for a Partner OS or RTOS
5.1.6. Choosing Boot Loader Software
5.1.7. Selecting Software Tools for Development, Debug and Trace
5.5.1.1. Enable Runtime Calibration Report
5.5.1.2. Change DLEVEL To Get More Debug Information
5.5.1.3. Enable Example Driver for HPS SDRAM
5.5.1.4. Change Data Pattern in Example Driver
5.5.1.5. Example Code to Write and Read from All Addresses
5.5.1.6. Read/Write to HPS Register in Preloader
5.5.1.7. Check HPS PLL Lock Status in Preloader
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5.3. SD Card Low Power Mode Design Considerations
The SD/MMC Controller has a low power mode which is enabled by setting the cclk_low_power bit of the clkena register to 1. When this mode takes effect, the clock to the card is disabled when the card is idle for at least eight card clock cycles.
During this low power mode, the state of the SD I/O signals are as follows:
- SD_CLK = 0
- SD_CMD = 1
- SD_D0..3 = floating
If the end application requires all SD I/O signals to be floating during the low power mode, the following procedure is recommended:
- When the card is not in use, after the last command:
- Set the GPIOs associated to the SD_CMD and SD_CLK pins as inputs by using the gpio registers.
- Change the pin muxing for the SD_CLK and SD_CMD pins to be GPIO signals by using the sysmgr.pinmux registers2.
- When the card is to be used again, before the next command:
- Change back the pin muxing for the SD_CLK and SD_CMD to be SD I/O signals by using the sysmgr.pinmux registers.
Note:
When the SD/MMC controller is in reset state, the state of the SD I/O signals is as follows:
- SD_CLK = 0
- SD_CMD = floating
- SD_D0..3 = floating