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1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
2. Background: Comparison between Cyclone® V SoC FPGA and Arria® V SoC FPGA HPS Subsystems
3. Design Guidelines for HPS portion of SoC FPGAs
4. Board Design Guidelines for SoC FPGAs
5. Embedded Software Design Guidelines for SoC FPGAs
A. Support and Documentation
B. Additional Information
3.6.1. Cache Coherency
3.6.2. Coherency between FPGA Logic and HPS: Accelerator Coherency Port (ACP)
3.6.3. Data Size Impacts ACP Performance
GUIDELINE: Use ACP for managing coherency for small data size accesses, manage coherency for large data in software.
3.6.4. Avoiding ACP Dependency Lockup
3.6.5. FPGA Access to ACP via AXI* or Avalon-MM
3.6.6. Data Alignment for ACP and L2 Cache ECC accesses
4.2.1.1. Boot Source
4.2.1.2. Select Desired Flash Device
4.2.1.3. BSEL Options
4.2.1.4. Boot Clock
4.2.1.5. CSEL Options
4.2.1.6. Selecting NAND Flash Devices
4.2.1.7. Determine Flash Programming Method
4.2.1.8. For QSPI and SD/MMC/eMMC Provide Flash Memory Reset
4.2.1.9. Selecting QSPI Flash Devices
4.5.1. HPS EMAC PHY Interfaces
4.5.2. USB Interface Design Guidelines
4.5.3. QSPI Flash Interface Design Guidelines
4.5.4. SD/MMC and eMMC Card Interface Design Guidelines
4.5.5. NAND Flash Interface Design Guidelines
4.5.6. UART Interface Design Guidelines
4.5.7. I2C Interface Design Guidelines
4.5.8. SPI Interface Design Guidelines
5.1.1. Assembling the Components of Your Software Development Platform
5.1.2. Selecting an Operating System for Your Application
5.1.3. Assembling your Software Development Platform for Linux
5.1.4. Assembling a Software Development Platform for a Bare-Metal Application
5.1.5. Assembling your Software Development Platform for a Partner OS or RTOS
5.1.6. Choosing Boot Loader Software
5.1.7. Selecting Software Tools for Development, Debug and Trace
5.5.1.1. Enable Runtime Calibration Report
5.5.1.2. Change DLEVEL To Get More Debug Information
5.5.1.3. Enable Example Driver for HPS SDRAM
5.5.1.4. Change Data Pattern in Example Driver
5.5.1.5. Example Code to Write and Read from All Addresses
5.5.1.6. Read/Write to HPS Register in Preloader
5.5.1.7. Check HPS PLL Lock Status in Preloader
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3.6.3. Data Size Impacts ACP Performance
Performance explorations of accelerators using ACP show that as size of packets transferred by AXI* master via the ACP port increases the accelerator performance increases but only up to a point. After that point, it is no longer possible to cache the entire data packet, and the accelerator suffers performance degradation.