Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

PLL Lock

The PLL lock is dependent on the two input signals in the phase frequency detector. The lock signal is an asynchronous output of the PLLs.

The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal.

Level Two Title