Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
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Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Building Blocks of a PLL

The main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter, VCO, and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters (C). The PLL architecture depends on the device you use in your design.

Figure 1. Typical PLL Architecture

The following terms are commonly used to describe the behavior of a PLL:

  • PLL lock time—also known as the PLL acquisition time. PLL lock time is the time for the PLL to attain the target frequency and phase relationship after power-up, after a programmed output frequency change, or after a PLL reset.
    Note: Simulation software does not model a realistic PLL lock time. Simulation shows an unrealistically fast lock time. For the actual lock time specification, refer to the device datasheet.
  • PLL resolution—the minimum frequency increment value of a PLL VCO. The number of bits in the M and N counters determine the PLL resolution value.
  • PLL sample rate—the FREF sampling frequency required to perform the phase and frequency correction in the PLL. The PLL sample rate is fREF /N.
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