Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Operation Modes

The Altera PLL IP core supports six different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and duty-cycle programming.

The following list describes the operation modes for the Altera PLL IP core:

  • Direct mode—the PLL minimizes the feedback path length to produce the smallest possible jitter at the PLL output. In this mode, the PLL does not compensate for any clock networks.
  • Normal mode—the PLL feedback path source is a global or regional clock network, minimizing clock delay from the input clock pin to the core registers through global or regional clock network.
  • Source-Synchronous mode—the data and clock signals arrive at the input pins at the same time. In this mode, the signals have the same phase relationship at the clock and data ports of any Input Output Enable register.
  • External Feedback mode—the PLL compensates for the fbclk feedback input to the PLL, thus minimizing the delay between the input clock pin and the feedback clock pin.
  • Zero-Delay Buffer mode—the PLL feedback path is confined to the dedicated PLL external output pin. The clock port driven off-chip is phase aligned with the clock input for a minimal delay between the clock input and the external clock output.
  • LVDS mode— maintains the same data and clock timing relationship of the pins at the internal SERDES capture register. This mode compensates for the LVDS clock network delay, plus any delay difference between the data pin and clock input pin to the SERDES capture register paths. The compensation mimic path mimics the clock and data delay of the receiver side.
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