JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683357
Date 11/22/2021
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

2.5. Compiling and Testing the Design

The JESD204C Intel® FPGA IP parameter editor allows you to run the design example on a target development kit.

Perform the following steps to compile the design and program the development board:

  1. Launch the Intel® Quartus® Prime software and compile the design (Processing > Start Compilation).
    The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
  2. Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
  3. Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
    Note: Refer to the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide for more information about using the Clock Control application.
    Table 8.  Clock Settings
    Clock Name Clock Frequency
    refclk_xcvr Select the frequency for the transceiver PLL reference clock in the IP parameter editor.
    refclk_core Select the frequency for the core PLL reference clock in the IP parameter editor.
    mgmt_clk 100 MHz
    Figure 5.  Intel® Stratix® 10 TX Signal Integrity Development Kit (Revision A or Revision B) Clock Control GUI Setting for Non-Bonded Mode DesignThis example shows the clock control GUI setting for a design example with non-bonded configuration. This design example is running at 24.333 Gbps on an E-tile device using Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit (applies to Revision A and Revision B).
    Figure 6.  Intel® Stratix® 10 TX Signal Integrity Development Kit (Revision B) Clock Control GUI Setting for Bonded Mode DesignThis example shows the clock control GUI setting for a design example with bonded configuration. This design example is running at 24.333 Gbps on an E-tile device using Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit (applies to Revision B).
  4. If you are performing external loopback test for designs targeting Intel® Stratix® 10 TX Signal Integrity Development Kit (E-tile), attach the respective loopback module according to the board revision and channel bonding mode:
    • For engineering sample (ES) edition (Revision A) and non-bonded configurations, attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector. Refer to Board Connectivity for information on which QSFP-DD 1x2 connectors to attach the module.
    • For production edition (Revision B) and non-bonded channel configuration, attach the FMC+ loopback module at the FMC+ connector.
    • For production edition (Revision B) and bonded channel configuration, attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector.
  5. Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.
To run the hardware testing using the Tcl script, refer to the Hardware Test for System Console Control Design Example section.
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