JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683357
Date 11/22/2021
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

2.3.2. Directory Structure

The JESD204C design example directories contain generated files for the design examples.
Figure 3. Directory Structure for JESD204C Intel® Stratix® 10 Design Example
Note: Intel® Stratix® 10 E-tile devices do not support Aldec Riviera-PRO* simulators.
Table 7.  Directory Files
Folders Files
ed/rtl
  • du
    • intel_j204c_ed_rx_tx.sv (top-level HDL file)
    • intel_j204c_ed_rx_tx.sdc
    • J204c_rx_tx_ip.qsys
    • j204c_rx_tx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • intel_j204c_se_outbuf_1bit.ip
  • rx
    • intel_j204c_ed_rx.sv (top-level HDL file)
    • intel_j204c_ed_rx.sdc
    • j204c_rx_ip.qsys
    • j204c_rx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • intel_j204c_se_outbuf_1bit.ip
  • tx
    • intel_j204c_ed_tx.sv (top-level HDL file)
    • intel_j204c_ed_tx.sdc
    • j204c_tx_ip.qsys
    • j204c_tx_ss.qsys
    • altera_s10_user_rst_clkgate_0.ip
    • intel_j204c_se_outbuf_1bit.ip
simulation/models
  • tb_top.sv
simulation/cadence
  • cadence_sim.sh
  • tb_top_wave.tcl
simulation/mentor
  • modelsim_sim.tcl
  • tb_top_waveform.do
simulation/synopsys
  • vcs
    • vcs_sim.sh
    • tb_top_wave_ed.do
  • vcsmx
    • vcsmx_sim.sh
    • tb_top_wave_ed.do
simulation/xcelium
  • xcelium_sim.sh
  • tb_top_wave.tcl
simulation/setup_scripts/common
  • modelsim_files.tcl
  • vcs_files.tcl
  • vcsmx_files.tcl
  • xcelium_files.tcl
simulation/setup_scripts/cadence
  • cds.lib
  • hdl.var
  • <cds_libs folder>
simulation/setup_scripts/mentor
  • msim_setup.tcl
simulation/setup_scripts/synopsys
  • vcs
    • vcs_setup.sh
  • vcsmx
    • vcsmx_setup.sh
    • synopsys_sim.setup
simulation/setup_scripts/xcelium
  • xcelium_setup.sh
  • cds.lib
  • hdl.var
  • <cds_libs folder>
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