AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

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ID 683347
Date 10/28/2020
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1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices x
1.1. Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IPs 1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs 1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IPs 1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel® FPGA IPs 1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs

The XAUI PHY Intel® FPGA IP provides an XGMII to Low Latency Ethernet 10G MAC Intel® FPGA IP and implements four lanes each at 3.125 Gbps at the PMD interface.

The XAUI PHY is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-2008 specification.

You can obtain the reference design for the 10GbE subsystem implemented using Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs from Design Store. The design supports functional simulation and hardware testing on designated Intel development kit.

Figure 4.  Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
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