AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

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ID 683347
Date 10/28/2020
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1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices x
1.1. Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IPs 1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs 1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IPs 1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel® FPGA IPs 1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IPs

The 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP provide MII, GMII and XGMII to Low Latency Ethernet 10G MAC Intel® FPGA IP.

The 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP implement a single-channel 10Mbps/100Mbps/1Gbps/10Gbps serial PHY. The designs provide a direct connection to 1G/10GbE dual speed SFP+ pluggable modules, 10M–10GbE 10GBASE-T and 10M/100M/1G/10GbE 1000BASE-T copper external PHY devices, or chip-to-chip interfaces. These IP cores support reconfigurable 10Mbps/100Mbps/1Gbps/10Gbps data rates.

Intel offers dual-speed 1G/10GbE and multi-speed 10Mb/100Mb/1Gb/10GbE design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kit.

The multi-speed Ethernet subsystem implementation using 1G/10GbE or 10GBASE-KR PHY Intel® Arria® 10 FPGA IP design requires manual SDC constraints for the internal PHY IP clocks and clock domain crossing handling. Refer to the altera_eth_top.sdc file in the design example to know more about the required create_generated_clock, set_clock_groups and set_false_path SDC constraints.

Figure 5.  Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel® Arria® 10 1G/10GbE and 10GBASE-KR Design Example (1G/10GbE Mode)
Figure 6.  Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel® Arria® 10 1G/10GbE and 10GBASE-KR Design Example (10Mb/100Mb/1Gb/10GbE Mode)
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