AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

Download PDF
ID 683347
Date 10/28/2020
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices x
1.1. Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IPs 1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel® FPGA IPs 1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel® Arria® 10 FPGA IPs 1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel® FPGA IPs 1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices

1.1. Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IPs

You can configure the Intel® Arria® 10 Transceiver Native PHY Intel® FPGA IP to implement the 10GBASE-R PHY with the Ethernet specific physical layer running at 10.3125 Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification.

This configuration provides an XGMII to Low Latency Ethernet 10G MAC Intel® FPGA IP and implements a single-channel 10.3 Gbps PHY providing a direct connection to an SFP+ optical module using SFI electrical specification.

Intel offers two 10GBASE-R Ethernet subsystem design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kits.

Figure 2. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY in 10GBASE-R Design Example
Figure 3. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel® Arria® 10 Transceiver Native PHY in 10GBASE-R Design Example with Register Mode Enabled
Related Information
Level Two Title