Visible to Intel only — GUID: bbz1503957727709
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: bbz1503957727709
Ixiasoft
Step 7: Compiling the Base Revision
- To compile the base revision, click Processing > Start Compilation. Alternatively, the following command compiles the base revision:
quartus_sh --flow compile blinking_led -c blinking_led
- Inspect the bitstream files generated to the output_files directory:
Table 5. Generated Files Name Type Description blinking_led.sof Base programming file For programming the FPGA with the static logic, along with the default personas for the parent and child PR regions. blinking_led.pr_parent_partition.rbf PR bitstream file for parent PR partition For programming the default persona of the parent PR region. blinking_led.pr_parent_partition.pr_partition.rbf PR bitstream file for child PR partition For programming the default persona of the child PR region. blinking_led_static.qdb .qdb database file Finalized database file for importing the static region. pr_parent_partition_default_final.qdb .qdb database file Finalized database file for importing the default parent PR partition.