AN 826: Hierarchical Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

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ID 683327
Date 1/05/2021
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 826: Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs connected to the FPGA. Selecting the output from particular counter bits causes the LEDs to blink at a specific frequency.

Figure 1. Flat Reference Design without PR Partitioning
Level Two Title