Visible to Intel only — GUID: ypp1503957708849
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: ypp1503957708849
Ixiasoft
Reference Design Requirements
This reference design requires the following:
- Intel® Quartus® Prime Pro Edition software version 20.3 for the design implementation.
- Intel® Stratix® 10 GX FPGA development kit (DK-DEV-1SGX-L-A or DK-DEV-1SGX-H-A) for the FPGA implementation.