AN 826: Hierarchical Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

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ID 683327
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 826: Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board

Modifying an Existing Persona

You can change an existing persona, even after fully compiling the base revision.

For example, to cause the blinking_led_child_slow persona to blink even slower:

  1. In the blinking_led_child_slow.sv file, modify the COUNTER_TAP parameter from 27 to 28.
  2. Recompile any implementation revision that uses this source file, such as hpr_child_slow or hpr_parent_slow_child_slow.
  3. Regenerate the PR bitstreams from the .pmsf files.
  4. Follow the steps in Step 10: Programming the Board to program the resulting RBF file into the FPGA.
Level Two Title