2. HDMI Design Example
The HDMI Intel® FPGA IP design example demonstrates one HDMI instance parallel loopback comprising three RX channels and four TX channels.
Design Example | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|
Cyclone 10 HDMI RX-TX Retransmit |
< 6,000 Mbps | Simplex | Parallel with FIFO buffer |
Features
- The design instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI sink and source.
- The design uses LED status for early debugging stage.
- The design comes with RX and TX only options.
- The design demonstrates the insertion and filtering of Dynamic Range and Mastering (HDR) InfoFrame in RX-TX link module.
- The design demonstrates the management of EDID passthrough from an external HDMI sink to an external HDMI source when triggered by a TX hot-plug event.
- The design allows run-time control through DIP switch and push-button to manage the HDMI TX core signals:
- mode signal to select DVI or HDMI encoded video frame
- info_avi[47], info_vsi[61], and audio_info_ai[48] signals to select auxiliary packet transmission through sidebands or auxiliary data ports
The RX instance receives a video source from the external video generator, and the data then goes through a loopback FIFO before it is transmitted to the TX instance. You need to connect an external video analyzer, monitor, or a television with HDMI connection to the TX core to verify the functionality.